Datasheet 74HCT4020N, 74HCT4020D, 74HCT4020U, 74HCT4020PW, 74HC4020U Datasheet (Philips)
...Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
September 1993
INTEGRATED CIRCUITS
74HC/HCT4020
14-stage binary ripple counter
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
Page 2
September 1993 2
Philips Semiconductors Product specification
14-stage binary ripple counter 74HC/HCT4020
FEATURES
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4020 are high-speed Si-gate CMOS
devices and are pin compatible with the “4020” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4020 are 14-stage binary ripple counters
with a clock input (
CP), an overriding asynchronous
master reset input (MR) and twelve fully buffered parallel
outputs (Q0, Q3to Q13).
The counter is advanced on the HIGH-to-LOW transition of
CP.
A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL/ tPLH
propagation delay CL= 15 pF; VCC=5 V
CP to Q
0
11 15 ns
Q
n
to Q
n+1
66ns
MR to Q
n
17 19 ns
f
max
maximum clock frequency 101 52 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per package notes 1 and 2 19 20 pF
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September 1993 3
Philips Semiconductors Product specification
14-stage binary ripple counter 74HC/HCT4020
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3 Q
0
, Q3to Q
13
parallel outputs
8 GND ground (0 V)
10
CP clock input (HIGH-to-LOW, edge-triggered)
11 MR master reset input (active HIGH)
16 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
page
MGA829
RCTR14
9
7
5
4
6
13
12
14
15
1
2
3
0
3
13
CT=0
CT
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September 1993 4
Philips Semiconductors Product specification
14-stage binary ripple counter 74HC/HCT4020
Fig.4 Functional diagram.
Fig.5 Logic diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH clock
transition
↓ = HIGH-to-LOW clock
transition
INPUTS OUTPUTS
CP MR Q0, Q3to Q
13
↑
↓
X
L
L
H
no change
count
L
Fig.6 Timing diagram.
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September 1993 5
Philips Semiconductors Product specification
14-stage binary ripple counter 74HC/HCT4020
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
CP to Q
0
39
14
11
140
28
24
175
35
30
210
42
36
ns 2.0
4.5
6.0
Fig.7
t
PHL
/ t
PLH
propagation delay
Qn to Q
n+1
22
8
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.7
t
PHL
propagation delay
MR to Q
n
55
20
16
170
34
29
215
43
37
225
51
43
ns 2.0
4.5
6.0
Fig.8
t
THL
/ t
TLH
output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.7
t
W
clock pulse width
HIGH or LOW
80
16
14
11
4
3
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.7
t
W
master reset pulse width
HIGH
80
16
14
17
6
5
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.8
t
rem
removal time
MR to CP
50
10
9
6
2
2
65
13
11
75
15
13
ns 2.0
4.5
6.0
Fig.8
f
max
maximum clock pulse
frequency
6.0
30
35
30
92
109
4.8
24
28
4.0
20
24
MHz 2.0
4.5
6.0
Fig.7
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September 1993 6
Philips Semiconductors Product specification
14-stage binary ripple counter 74HC/HCT4020
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
CP
MR
0.85
1.10
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
CP to Q
0
18 36 45 54 ns 4.5 Fig.7
t
PHL
/ t
PLH
propagation delay
Qn to Q
n+1
8 15 19 22 ns 4.5 Fig.7
t
PHL
propagation delay
MR to Q
n
22 45 56 68 ns 4.5 Fig.8
t
THL
/ t
TLH
output transition time 7 15 19 22 ns 4.5 Fig.7
t
W
clock pulse width
HIGH or LOW
20 7 25 30 ns 4.5 Fig.7
t
W
master reset pulse width
HIGH
20 8 25 30 ns 4.5 Fig.8
t
rem
removal time
MR to CP
10 2 13 15 ns 4.5 Fig.8
f
max
maximum clock pulse
frequency
25 47 20 17 MHz 4.5 Fig.7
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September 1993 7
Philips Semiconductors Product specification
14-stage binary ripple counter 74HC/HCT4020
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.7 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.8 Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays
and the master reset to clock (CP) removal time.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
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