Datasheet 74HCT4015D, 74HCT4015U, 74HCT4015N, 74HC4015U, 74HC4015N Datasheet (Philips)

DATA SH EET

Product specification
File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT4015

Dual 4-bit serial-in/parallel-out shift
register

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2

Philips Semiconductors Product specification

Dual 4-bit serial-in/parallel-out shift
register

74HC/HCT4015

FEATURES

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4015 are high-speed Si-gate CMOS
devices and are pin compatible with the “4015” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.

The 74HC/HCT4015 are dual edge-triggered 4-bit static
shift registers (serial-to-parallel converters). Each shift
register has a serial data input (1D and 2D), a clock input
(1CP and 2CP), four fully buffered parallel outputs (1Q

0

to
1Q3 and 2Q0 to 2Q3) and an overriding asynchronous
master reset (1MR and 2MR). Information present on nD
is shifted to the first register position, and all data in the
register is shifted one position to the right on the
LOW-to-HIGH transition of nCP.
A HIGH on nMR clears the register and forces nQ0 to nQ

3

to LOW, independent of nCP and nD.

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C; tr=tf= 6 ns

Notes

1. C

PD

is used to determine the dynamic power dissipation (PD in µW):

PD=CPD× V

CC

2

× fi+∑(CL× V

CC

2

× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

CC

2

× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

t

PHL

/ t

PLH

propagation delay nCP to nQ

n

CL= 15 pF; VCC=5 V1618ns

f

max

maximum clock frequency 110 74 MHz

C

I

input capacitance 3.5 3.5 pF

C

PD

power dissipation capacitance per register notes 1 and 2 35 40 pF

December 1990 3

Philips Semiconductors Product specification

Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

5, 4, 3, 10 1Q

0

to 1Q

3

flip-flop outputs
6, 14 1MR, 2MR asynchronous master reset inputs (active HIGH)
7, 15 1D, 2D serial data inputs
8 GND ground (0 V)
9, 1 1CP, 2CP clock inputs (LOW-to-HIGH, edge-triggered)
13, 12, 11, 2 2Q

0

to 2Q

3

flip-flop outputs
16 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 4

Philips Semiconductors Product specification

Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015

Fig.4 Functional diagram.

Fig.5 Logic diagram (one 4-bit

serial-in/parallel-out shift register).

FUNCTION TABLE

Notes

1. H = HIGH voltage level
L = LOW voltage level
X = don’t care

↑ = LOW-to-HIGH clock transition
↓ = HIGH-to-LOW clock transition

n = number of clock pulse transitions
D

n

= either HIGH or LOW

APPLICATIONS

• Serial-to-parallel converter

• Buffer stores

• General purpose register

INPUTS OUTPUTS

n nCP nD nMR nQ

0

nQ1nQ2nQ

3

1
2
3
4

↑
↑
↑
↑

D

1

D

2

D

3

D

4

L
L
L
L

D

1

D

2

D

3

D

4

X
D

1

D

2

D

3

X
X
D

1

D

2

X
X
X
D

1

↓ X L no change
XXHLLLL

December 1990 5

Philips Semiconductors Product specification

Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

.

Output capability: standard
ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

r=tf

= 6 ns; CL= 50 pF

SYMBOL

PARAMETER

T

amb

(°C)

UNIT

TEST CONDITIONS

74HC

V

CC

(V)

WAVEFORMS

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

t

PHL

/ t

PLH

propagation delay

nCP to nQ

n

52
19
15

175
35
30

220
44
37

265
53
45

ns 2.0

4.5

6.0

Fig.6

t

PHL

propagation delay

nMR to nQ

n

44
16
13

175
35
30

220
44
37

265
53
45

ns 2.0

4.5

6.0

Fig.7

t

THL

/ t

TLH

output transition time 19

7
6

75
15
13

95
19
16

110
22
19

ns 2.0

4.5

6.0

Fig.6

t

W

clock pulse width

HIGH or LOW

80
16
14

17
6
5

100
20
17

120
24
20

ns 2.0

4.5

6.0

Fig.6

t

W

master reset pulse
width HIGH

80
16
14

17
6
5

100
20
17

120
24
20

ns 2.0

4.5

6.0

Fig.7

t

rem

removal time

nMR to nCP

60
12
10

17
6
5

75
15
13

90
18
15

ns 2.0

4.5

6.0

Fig.7

t

su

set-up time

nD to nCP

60
12
10

8
3
2

75
15
13

90
18
15

ns 2.0

4.5

6.0

Fig.8

t

h

hold time

nD to nCP

5
5
5

0
0
0

5
5
5

5
5
5

ns 2.0

4.5

6.0

Fig.8

f

max

maximum clock pulse

frequency

6.0
30
35

33
100
119

4.8
24
28

4.0
20
24

MHz 2.0

4.5

6.0

Fig.6

December 1990 6

Philips Semiconductors Product specification

Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

.

Output capability: standard
ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆I

CC

) for a unit load of 1 is given in the family specifications.

To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

r=tf

= 6 ns; CL= 50 pF

INPUT UNIT LOAD COEFFICIENT

nD
nMR
nCP

0.30

1.50

1.50

SYMBOL PARAMETER

T

amb

(°C) TEST CONDITIONS

74HCT

UNIT

V

CC

(V)

WAVEFORMS

+25 −40 to +85 −40

to +125

min. typ. max. min. max. min. max.

t

PHL

/ t

PLH

propagation delay

nCP to nQ

n

21 35 44 53 ns 4.5 Fig.6

t

PHL

propagation delay

nMR to nQ

n

18 35 44 53 ns 4.5 Fig.7

t

THL

/ t

TLH

output transition time 7 15 19 22 ns 4.5 Fig.6

t

W

clock pulse width

HIGH or LOW

16 7 20 24 ns 4.5 Fig.6

t

W

master reset pulse width

HIGH

16 5 20 24 ns 4.5 Fig.7

t

rem

removal time

nMR to nCP

20 10 25 30 ns 4.5 Fig.7

t

su

set-up time

nD to nCP

12 4 15 18 ns 4.5 Fig.8

t

h

hold time

nD to nCP

5 −2 5 5 ns 4.5 Fig.8

f

max

maximum clock pulse

frequency

30 67 24 20 MHz 4.5 Fig.6

December 1990 7

Philips Semiconductors Product specification

Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015

AC WAVEFORMS

Fig.6 Waveforms showing the clock (nCP) to output (nQn) propagation delays, the clock pulse width, the output

transition times and the maximum clock frequency.

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

M

= 1.3 V; VI= GND to 3 V.

Fig.7 Waveforms showing the master reset (nMR) pulse width, the master reset to output (nQn) propagation

delay and the master reset to clock (nCP) removal time.

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

M

= 1.3 V; VI= GND to 3 V.

Fig.8 Waveforms showing the data set-up and hold times for nD inputs.

The shaded areas indicate when the input is permitted to
change for predictable output performance.

(1) HC : V

M

= 50%; VI= GND to VCC.

HCT: V

M

= 1.3 V; VI= GND to 3 V.

December 1990 8

Philips Semiconductors Product specification

Dual 4-bit serial-in/parallel-out shift register 74HC/HCT4015

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

.