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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT393
Dual 4-bit binary ripple counter
Product specification
File under Integrated Circuits, IC06
December 1990
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Philips Semiconductors Product specification
Dual 4-bit binary ripple counter 74HC/HCT393
FEATURES
• Two 4-bit binary counters with individual clocks
• Divide-by any binary module up to 28 in one package
• Two master resets to clear each 4-bit counter
individually
• Output capability: standard
• ICC category: MSI
The 74HC/HCT393 are 4-bit binary ripple counters with
separate clocks (1
and 2MR) inputs to each counter. The operation of each
half of the “393” is the same as the “93” except no external
clock connections are required.
The counters are triggered by a HIGH-to-LOW transition of
the clock inputs. The counter outputs are internally
connected to provide clock inputs to succeeding stages.
The outputs of the ripple counter do not change
synchronously and should not be used for high-speed
GENERAL DESCRIPTION
The 74HC/HCT393 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
address decoding.
The master resets are active-HIGH asynchronous inputs
to each 4-bit counter identified by the “1” and “2” in the pin
description.
A HIGH level on the nMR input overrides the clock and
sets the outputs LOW.
QUICK REFERENCE DATA
GND = 0 V; T
= 25 °C; tr= tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
f
max
C
C
I
PD
/ t
PLH
propagation delay CL= 15 pF; VCC= 5 V
n
CP to nQ
nQ to nQ
nMR to nQ
0
n+1
n
maximum clock frequency 99 53 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per counter notes 1 and 2 23 25 pF
CP and 2 CP) and master reset (1MR
TYPICAL
UNIT
HC HCT
12 20 ns
56ns
11 15 ns
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW):
PD
PD= CPD× V
2
× fi+∑(CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
December 1990 2
.
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Philips Semiconductors Product specification
Dual 4-bit binary ripple counter 74HC/HCT393
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 13 1
2, 12 1MR, 2MR asynchronous master reset inputs (active HIGH)
3, 4, 5, 6, 11, 10, 9, 8 1Q
7 GND ground (0 V)
14 V
CP, 2CP clock inputs (HIGH-to-LOW, edge-triggered)
to 1Q3, 2Q0to 2Q
0
CC
3
flip-flop outputs
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
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Philips Semiconductors Product specification
Dual 4-bit binary ripple counter 74HC/HCT393
Fig.4 Functional diagram. Fig.5 State diagram.
COUNT SEQUENCE FOR 1 COUNTER
OUTPUTS
COUNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Q
0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Q
1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
Q
2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
Q
3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Fig.6 Logic diagram (one counter).
December 1990 4
Notes
1. H = HIGH voltage level
L = LOW voltage level
Page 5
Philips Semiconductors Product specification
Dual 4-bit binary ripple counter 74HC/HCT393
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICCcategory: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
SYMBOL PARAMETER
/ t
t
PHL
PLH
t
/ t
PHL
PLH
t
PHL
t
/ t
THL
TLH
t
W
= tf= 6 ns; CL= 50 pF
r
propagation delay
nCP to nQ
0
propagation delay
nQnto nQ
n+1
propagation delay
nMR to nQ
n
output transition time 19
clock pulse width
HIGH or LOW
t
W
master reset pulse
width; HIGH
t
rem
removal time
nMR to nCP
f
max
maximum clock pulse
frequency
T
(°C)
amb
74HC
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
41
80
16
14
80
16
14
5
5
5
6
30
35
15
12
14
5
4
39
14
11
7
6
17
6
5
19
7
6
3
1
1
30
90
107
125
25
21
45
9
8
140
28
24
75
15
13
100
20
17
100
20
17
5
5
5
5
24
28
155
31
26
55
11
9
175
35
30
95
19
16
190
38
32
70
14
12
210
42
36
110
22
19
120
24
20
120
24
20
5
5
5
4
20
24
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
MHz 2.0
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.8
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.8
4.5
6.0
Fig.8
4.5
6.0
Fig.7
4.5
6.0
December 1990 5
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Philips Semiconductors Product specification
Dual 4-bit binary ripple counter 74HC/HCT393
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICCcategory: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
) for a unit load of 1 is given in the family specifications.
CC
To determine ∆ICCper input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
CP
1
2CP
1MR
2MR
0.4
0.4
1.0
1.0
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
T
amb
(°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
+25 −40 to +85 −40 to +125
UNIT
V
(V)
min. typ. max. min. max. min. max.
t
PHL
t
PHL
t
PHL
t
THL
/ t
/ t
/ t
propagation delay
PLH
nCP to nQ
propagation delay
PLH
nQnto nQ
0
n+1
propagation delay
nMR to nQ
output transition time 7 15 19 22 ns 4.5 Fig.7
TLH
n
15 25 31 38 ns 4.5 Fig.7
6 10 13 15 ns 4.5 Fig.7
18 32 40 48 ns 4.5 Fig.8
WAVEFORMS
CC
t
W
clock pulse width
19 11 24 29 ns 4.5 Fig.7
HIGH or LOW
t
W
master reset pulse
16 6 20 24 ns 4.5 Fig.8
width; HIGH
t
rem
removal time
5 0 5 5 ns 4.5 Fig.8
nMR to nCP
f
max
maximum clock pulse
27 48 22 18 MHz 4.5 Fig.7
frequency
December 1990 6
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Philips Semiconductors Product specification
Dual 4-bit binary ripple counter 74HC/HCT393
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.7 Waveforms showing the clock (nCP) to output (1Qn,2Qn) propagation delays, the clock pulse width, the
output transition times and the maximum clock frequency.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.8 Waveforms showing the master reset (nMR) pulse width, the master reset to output (Qn) propagation
delays and the master reset to clock (nCP) removal time.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 7
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