Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT365
Hex buffer/line driver; 3-state
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
Page 2
December 1990 2
Philips Semiconductors Product specification
Hex buffer/line driver; 3-state 74HC/HCT365
FEATURES
• Non-inverting outputs
• Output capability: bus driver
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT365 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT365 are hex non-inverting buffer/line
drivers with 3-state outputs. The 3-state outputs (nY) are
controlled by the output enable inputs (
OE1, OE2).
A HIGH on OEn causes the outputs to assume a high
impedance OFF-state.
The “365” is identical to the “366” but has non-inverting
outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi + ∑ (CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay
nA to nY
CL= 15 pF; VCC=5 V 9 11 ns
C
I
input capacitance 3,5 3,5 pF
C
PD
power dissipation capacitance per buffer notes 1 and 2 40 40 pF
Page 3
December 1990 3
Philips Semiconductors Product specification
Hex buffer/line driver; 3-state 74HC/HCT365
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 15
OE1, OE
2
output enable inputs (active LOW)
2, 4, 6, 10, 12, 14 1A to 6A data inputs
3, 5, 7, 9, 11, 13 1Y to 6Y data outputs
8 GND ground (0 V)
16 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Fig.3 IEC logic symbol.
Page 4
December 1990 4
Philips Semiconductors Product specification
Hex buffer/line driver; 3-state 74HC/HCT365
Fig.4 Functional diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
INPUTS OUTPUT
OE
1
OE
2
nA nY
L
L
X
H
L
L
H
X
L
H
X
X
L
H
Z
Z
Fig.5 Logic diagram.
Page 5
December 1990 5
Philips Semiconductors Product specification
Hex buffer/line driver; 3-state 74HC/HCT365
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to+85 −40 to+125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nA to nY
30
11
9
95
19
16
120
24
20
145
29
25
ns 2.0
4.5
6.0
Fig.6
t
PZH
/ t
PZL
3-state output enable time
OEn to nY
47
17
14
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.7
t
PHZ
/ t
PLZ
3-state output disable
time
OEn to nY
61
22
18
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.7
t
THL
/ t
TLH
output transition time 14
5
4
60
12
10
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.6
Page 6
December 1990 6
Philips Semiconductors Product specification
Hex buffer/line driver; 3-state 74HC/HCT365
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
OE
1
OE
2
nA
1.00
0.90
1.00
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25 −40 to+85 −40 to+125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nA to nY
14 25 31 38 ns 4.5 Fig.6
t
PZH
/ t
PZL
3-state output enable
time
OEn to nY
18 35 44 53 ns 4.5 Fig.7
t
PHZ
/ t
PLZ
3-state output disable
time
OEn to nY
23 35 44 53 ns 4.5 Fig.7
t
THL
/ t
TLH
output transition time 5 12 15 18 ns 4.5 Fig.6
Page 7
December 1990 7
Philips Semiconductors Product specification
Hex buffer/line driver; 3-state 74HC/HCT365
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.6 Waveforms showing the input (nA) to output (nY) propagation delays and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the 3-state enable and disable times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
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