Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT32
Quad 2-input OR gate
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
Page 2
December 1990 2
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC/HCT32
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT32 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT32 provide the 2-input OR function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf=6ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi+∑(CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay nA, nB to nY CL = 15 pF; VCC=5V 6 9 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per gate notes 1 and 2 16 28 pF
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December 1990 3
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC/HCT32
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 4, 9, 12 1A to 4A data inputs
2, 5, 10, 13 1B to 4B data inputs
3, 6, 8, 11 1Y to 4Y data outputs
7 GND ground (0 V)
14 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
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December 1990 4
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC/HCT32
Fig.4 Functional diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
INPUTS OUTPUT
nA nB nY
L
L
H
H
L
H
L
H
L
H
H
H
Fig.5 Logic diagram 74HC (one gate). Fig.6 Logic diagram 74HCT (one gate).
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December 1990 5
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC/HCT32
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r=tf
= 6 ns; CL=50pF
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: SSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r=tf
= 6 ns; CL=50pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nA, nB to nY
22
8
6
90
18
15
115
23
20
135
27
23
ns 2.0
4.5
6.0
Fig.7
t
THL
/ t
TLH
output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.7
INPUT UNIT LOAD COEFFICIENT
nA, nB 1.20
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nA, nB to nY
11 24 30 36 ns 4.5 Fig.7
t
THL
/ t
TLH
output transition time 7 15 19 22 ns 4.5 Fig.7
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December 1990 6
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC/HCT32
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.7 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
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