Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
September 1993
INTEGRATED CIRCUITS
74HC/HCT273
Octal D-type flip-flop with reset;
positive-edge trigger
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
Page 2
September 1993 2
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74HC/HCT273
FEATURES
• Ideal buffer for MOS microprocessor or memory
• Common clock and master reset
• Eight positive edge-triggered D-type flip-flops
• See “377” for clock enable version
• See “373” for transparent latch version
• See “374” for 3-state version
• Output capability; standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT273 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT273 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The
common clock (CP) and master reset (MR) inputs load and
reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.
All outputs will be forced LOW independently of clock or
data inputs by a LOW voltage level on the MR input.
The device is useful for applications where the true output
only is required and the clock and master reset are
common to all storage elements.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL/ tPLH
propagation delay CL= 15 pF; VCC=5 V
CP to Q
n
15 15 ns
MR to Q
n
15 20 ns
f
max
maximum clock frequency 66 36 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per flip-flop notes 1 and 2 20 23 pF
Page 3
September 1993 3
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74HC/HCT273
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
MR master reset input (active LOW)
2, 5, 6, 9, 12, 15, 16, 19 Q
0
to Q
7
flip-flop outputs
3, 4, 7, 8, 13, 14, 17, 18 D
0
to D
7
data inputs
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH, edge-triggered)
20 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Page 4
September 1993 4
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74HC/HCT273
Fig.4 Functional diagram.
FUNCTION TABLE
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
↑ = LOW-to-HIGH transition
X = don’t care
OPERATING
MODES
INPUTS OUTPUTS
MR CP D
n
Q
n
reset (clear) L X X L
load “1” H ↑ hH
load “0” H ↑ IL
Fig.5 Logic diagram.
Page 5
September 1993 5
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74HC/HCT273
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
41
15
13
150
30
26
185
37
31
225
45
38
ns 2.0
4.5
6.0
Fig.6
t
PHL
propagation delay
MR to Q
n
44
16
14
150
30
26
185
37
31
225
45
38
ns 2.0
4.5
6.0
Fig.7
t
THL
/ t
TLH
output transition time 19
7
6
75
15
13
95
19
15
110
22
19
ns 2.0
4.5
6.0
Fig.6
t
W
clock pulse width
HIGH or LOW
80
16
14
14
5
4
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.6
t
W
master reset pulse width
LOW
60
12
10
17
6
5
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.7
t
rem
removal time
MR to CP
50
10
9
−6
−2
−2
65
13
11
75
15
13
ns 2.0
4.5
6.0
Fig.7
t
su
set-up time
Dn to CP
60
12
10
11
4
3
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.8
t
h
hold time
Dn to CP
3
3
3
−6
−2
−2
3
3
3
3
3
3
ns 2.0
4.5
6.0
Fig.8
f
max
maximum clock pulse
frequency
6.0
30
35
20.6
103
122
4.8
24
28
4.0
20
24
MHz 2.0
4.5
6.0
Fig.6
Page 6
September 1993 6
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74HC/HCT273
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
MR
CP
D
n
1.00
1.75
0.15
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
16 30 38 45 ns 4.5 Fig.6
t
PHL
propagation delay
MR to Q
n
23 34 43 51 ns 4.5 Fig.7
t
THL
/ t
TLH
output transition time 7 15 19 22 ns 4.5 Fig.6
t
W
clock pulse width
HIGH or LOW
16 9 20 24 ns 4.5 Fig.6
t
W
master reset pulse width
LOW
16 8 20 24 ns 4.5 Fig.7
t
rem
removal time
MR to CP
10 −2 13 15 ns 4.5 Fig.7
t
su
set-up time
Dn to CP
12 5 15 18 ns 4.5 Fig.8
t
h
hold time
Dn to CP
3 −4 3 3 ns 4.5 Fig.8
f
max
maximum clock pulse
frequency
30 56 24 20 MHz 4.5 Fig.6
Page 7
September 1993 7
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74HC/HCT273
AC WAVEFORMS
Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width output
transition times and the maximum clock pulse frequency.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays
and the master reset to clock (CP) removal time.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.8 Waveforms showing the data set-up and hold times for the data input (Dn).
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
M
= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Page 8
September 1993 8
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
74HC/HCT273
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
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