Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT251
8-input multiplexer; 3-state
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
Page 2
December 1990 2
Philips Semiconductors Product specification
8-input multiplexer; 3-state 74HC/HCT251
FEATURES
• True and complement outputs
• Both outputs are 3-state for further multiplexer
expansion
• Multifunction capability
• Permits multiplexing from n-lines to one line
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT251 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT251 are the logic implementations of
single-pole 8-position switches with the state of three
select inputs (S
0,S1,S2
) controlling the switch positions.
Assertion (Y) and negation (Y) outputs are both provided.
The output enable input (OE) is active LOW. The logic
function provided at the output, when activated, is:
Y=OE.(I0.S0.S1.S2 + I1.S0.S1.S2+
+ I2.S0.S1.S2+ I3.S0.S1.S2+
+ I4.S0.S1.S2+ I5.S0.S1.S2+
+ I6.S0.S1.S2+ I7.S0.S1.S2)
Both outputs are in the high impedance OFF-state (Z)
when the output enable input is HIGH, allowing multiplexer
expansion by tying the outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25 °C; tr= tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PDin µW):
PD= CPD× V
CC
2
× fi+∑(CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay CL= 15 pF; VCC= 5 V
I
n
to Y 15 19 ns
I
n
to Y1719ns
S
n
to Y 20 20 ns
S
n
to Y2121ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per package notes 1 and 2 44 46 pF
Page 3
December 1990 3
Philips Semiconductors Product specification
8-input multiplexer; 3-state 74HC/HCT251
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
4, 3, 2, 1, 15, 14, 13, 12 I
0
to I
7
multiplexer inputs
5 Y multiplexer output
6
Y complementary multiplexer output
7
OE 3-state output enable input (active LOW)
8 GND ground (0 V)
11, 10, 9 S
0,S1,S2
select inputs
16 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Page 4
December 1990 4
Philips Semiconductors Product specification
8-input multiplexer; 3-state 74HC/HCT251
FUNCTION TABLE
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
INPUTS OUTPUTS
OE S
2
S
1
S
0
I
0
I
1
I
2
I
3
I
4
I
5
I
6
I
7
YY
HXXXXXXXXXXXZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
X
X
X
X
X
X
X
X
L
H
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
L
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
L
H
X
X
X
X
X
X
X
X
H
L
H
L
L
H
L
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
L
H
H
L
H
L
L
H
L
H
Fig.4 Functional diagram. Fig.5 Logic diagram.
Page 5
December 1990 5
Philips Semiconductors Product specification
8-input multiplexer; 3-state 74HC/HCT251
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICCcategory: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= tf= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
Into Y
50
18
14
170
34
29
215
43
37
255
51
43
ns 2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
Into Y
55
20
16
175
35
30
220
44
37
265
53
45
ns 2.0
4.5
6.0
Fig.7
t
PHL
/ t
PLH
propagation delay
Snto Y
66
24
19
205
41
35
255
51
43
310
62
53
ns 2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
Snto Y
69
25
20
205
41
35
255
51
43
310
62
53
ns 2.0
4.5
6.0
Fig.7
t
PZH
/ t
PZL
3-state output enable time
OE to Y, Y
36
13
10
140
28
24
175
35
30
210
42
36
ns 2.0
4.5
6.0
Fig.7
t
PHZ
/ t
PLZ
3-state output disable time
OE to Y, Y
39
14
11
140
28
24
170
35
30
210
42
36
ns 2.0
4.5
6.0
Fig.7
t
THL
/ t
TLH
output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Figs 6 and 7
Page 6
December 1990 6
Philips Semiconductors Product specification
8-input multiplexer; 3-state 74HC/HCT251
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICCcategory: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICCper input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR HCT
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
I
n
S
0
S1,S
2
OE
1.00
1.50
1.50
1.50
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
Into Y
22 35 44 53 ns 4.5 Fig.6
t
PHL
/ t
PLH
propagation delay
Into Y
22 35 44 53 ns 4.5 Fig.7
t
PHL
/ t
PLH
propagation delay
Snto Y
24 44 55 66 ns 4.5 Fig.6
t
PHL
/ t
PLH
propagation delay
Snto Y
25 44 55 66 ns 4.5 Fig.7
t
PZH
/ t
PZL
3-state output enable time
OE to Y, Y
13 28 35 42 ns 4.5 Fig.7
t
PHZ
/ t
PLZ
3-state output disable time
OE to Y, Y
14 28 35 42 ns 4.5 Fig.7
t
THL
/ t
TLH
output transition time 7 15 19 22 ns 4.5 Figs 6 and 7
Page 7
December 1990 7
Philips Semiconductors Product specification
8-input multiplexer; 3-state 74HC/HCT251
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.6 Waveforms showing the multiplexer input (In) and select input (Sn) to output (Y) propagation delays and
the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3V; VI= GND to 3 V.
Fig.7 Waveforms showing the multiplexer input (In) and select input (Sn) to output (Y) propagation delays and
the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3V; VI= GND to 3 V.
Fig.8 Waveforms showing the 3-state enable and disable times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3V; VI= GND to 3 V.
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