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MM74HC240
Inverting Octal 3-STATE Buffer
MM74HC240 Inverting Octal 3-STATE Buffer
September 1983
Revised August 2000
General Description
The MM74HC240 3-STATE buffer utilizes advanced silicon-gate CMOS techno logy. It possesses high drive current outputs which enable high speed operation even when
driving large bus capacitances. These circuits achieve
speeds comparable to low power Schottky devices, while
retaining the advanta ge of CMOS cir cuitry, i.e., high noise
immunity and low power consumption. It has a fanout of 15
LS-TTL equivalent inputs.
The MM74HC240 is an inve rting b uffer and ha s two a ctive
LOW enables (1G
controls 4 buffers.
All inputs are protected from damage due to static discharge by diodes to V
and 2G). Each enable independently
and ground.
CC
Features
■ Typical propagation delay: 12 ns
■ 3-STATE outputs for connection to system buses
■ Wide power supply range: 2–6V
■ Low quiescent supply current: 80
■ Output current: 6 mA
µA (74 Series)
Ordering Code:
Order Number Package Number Package Description
MM74HC240WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
MM74HC240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC240N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also availab l e in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram
Truth Table
1G 1A 1Y 2G 2A 2Y
LLHLLH
LHLLHL
HLZHLZ
HHZHHZ
H = HIGH Level
L = LOW Level
Z = HIGH Impedance
Top View
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Logic Diagram
MM74HC240
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Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
DC Output Voltage (V
Clamp Diode Current (I
DC Output Current, per pin (I
DC V
or GND Current, per pin (ICC) ±70 mA
CC
Storage Temperature Range (T
Power Dissipation (P
) −1.5 to V
IN
) −0.5 to V
OUT
, IOK) ±20 mA
IK
) ±35 mA
OUT
) −65°C to +150°C
STG
)
D
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
)
L
(Soldering 10 seconds) 260
CC
CC
+1.5V
+0.5V
Recommended Operating
Conditions
Min Max Units
Supply Voltage (V
DC Input or Output Voltage 0 V
, V
(V
IN
OUT
Operating Temperature Range (T
Input Rise or Fall Times
, tf) V
(t
r
CC
V
= 4.5V 500 ns
CC
V
= 6.0V 400 ns
CC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: unless otherw ise specified all voltages are referenced to ground.
°C
Note 3: Power Dissipat ion temp er atur e derat ing — pla st ic “N” package: −
12 mW/°C from 65°C to 85°C.
)26V
CC
)
) −40 +85 °C
A
= 2.0V 1000 ns
CC
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions
V
V
V
V
I
I
I
Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
Maximum LOW Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage 4.5V 1.35 1.35 1.35 V
Minimum HIGH Level V
OH
Output Voltage |I
Maximum LOW Level V
OL
Output Voltage |I
Maximum Input Current V
IN
Maximum 3-STATE V
OZ
Output Leakage V
Current G = VIH, G = V
Maximum Quiescent V
CC
Supply Current I
Note 4: For a power supply of 5V ±10% the worst ca se o utpu t volt ages (VOH, and VOL) occur for HC at 4.5 V. Thus the 4.5V val ues shou ld be us ed w hen
designing with this supply. Worst case V
, ICC, and IOZ) occur for CMOS at the higher voltage and so th e 6. 0V values should be used.
rent (I
IN
= VIH or V
I N
OUT
V
IN
|I
OUT
|I
OUT
IN
OUT
V
IN
|I
OUT
|I
OUT
IN
IN
OUT
IN
OUT
and VIL occur at V
IH
IL
| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
= VIH or V
IL
| ≤ 6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
| ≤ 7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
= VIH or V
IL
| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
= VIH or V
IL
| ≤ 6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
| ≤ 7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
= VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
= VIH or V
IL
= VCC or GND 6.0V ±0.5 ±5 ±10 µA
IL
= VCC or GND
= 0 µA
CC
V
CC
6.0V 4.2 4.2 4.2 V
6.0V 1.8 1.8 1.8 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
6.0V 8.0 80 160 µA
= 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Typ Guaranteed Limits
MM74HC240
V
Units
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AC Electrical Characteristics
V
= 5V, TA = 25°C, tr = tf = 6 ns
CC
Symbol Parameter Conditions Typ Guaranteed Limit Units
, t
t
PHL
MM74HC240
t
PZH
t
PHZ
Maximum Propagation Delay CL = 45 pF 12 18 ns
PLH
, t
Maximum Enable Delay RL = 1 kΩ
PZL
to Active Output C
, t
Maximum Disable Delay RL = 1 kΩ
PLZ
from Active Output CL = 5 pF
= 45 pF
L
14 28 ns
13 25 ns
AC Electrical Characteristics
V
= 2.0V to 6.0V, C
CC
Symbol Parameter Conditions
t
, t
Maximum Propagation CL = 50 pF 2.0V 55 100 126 149 ns
PHL
PLH
Delay C
t
, t
Maximum Output Enable RL = 1 kΩ
PZH
PZL
TIme C
t
, t
Maximum Output Disable RL = 1 kΩ 2.0V 75 150 189 224 ns
PHZ
PLZ
Time CL = 50 pF 4.5V 15 30 38 45 ns
t
, t
Maximum Output 2.0V 60 75 90 ns
TLH
THL
Rise and Fall Time 4.5V 12 15 18 ns
C
Power Dissipation (per buffer)
PD
Capacitance (Note 5) G = V
C
C
Maximum Input Capacitance 5 10 10 10 pF
IN
Maximum Output Capacitance 10 20 20 20 pF
OUT
Note 5: CPD determines the no lo ad dynamic power consumption, PD = CPD V
= CPDVCCf + ICC.
I
S
= 50 pF, t
L
= tf = 6 ns (unless otherwise specified)
r
V
CC
= 150 pF 2.0V 80 150 190 224 ns
L
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Typ Guaranteed Limits
CL = 50 pF 4.5V 12 20 25 30 ns
CL = 150 pF 4.5V 22 30 38 45 ns
CL = 50 pF 6.0V 11 17 21 25 ns
CL = 150 pF 6.0V 28 26 32 38 ns
= 50 pF 2.0V 75 150 189 224 ns
L
CL = 150 pF 2.0V 100 200 252 298 ns
CL = 50 pF 4.5V 15 30 38 45 ns
CL = 150 pF 4.5V 20 40 50 60 ns
CL = 50 pF 6.0V 13 26 32 38 ns
CL = 150 pF 6.0V 17 34 43 51 ns
6.0V 13 26 32 38 ns
6.0V 10 13 15 ns
IH
G
= V
IL
12 pF
50 pF
2
f + ICC VCC, and the no load dynamic current consumption,
CC
Units
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Physical Dimensions inches (millimeters) unless otherwise noted
MM74HC240
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
5 www.fairchildsemi.com
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
MM74HC240
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
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Package Number M20D
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
MM74HC240
20-Lead Thin Shrin k Small Ou tlin e Pack age (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
MM74HC240 Inverting Octal 3-STATE Buffer
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied a nd
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are device s or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
Package Number N20A
2. A critical component in any compon ent of a l ife supp ort
device or system whose failu re to perform can be reasonably expected to cause the failure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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