Datasheet 74HC 221 Datasheet (FREI)

Data sheet acquired from Harris Semiconductor

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SCHS166F

November 1997 - Revised October 2003

CD54HC221, CD74HC221,

CD74HCT221

High-Speed CMOS Logic

Dual Monostable Multivibrator with Reset

/Title
CD74

C221

D74
CT22

)
Sub­ect
High

peed

MOS

ogic

ual

onos

able

ulti-

Features

• Overriding RESET Terminates Output Pulse

• Triggering from the Leading or Trailing Edge

• Q and

• Separate Resets

• Wide Range of Output-Pulse Widths

• Schmitt Trigger on B Inputs

• Fanout (Over Temperature Range)

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

• HC Types

• HCT Types

Q Buffered Outputs

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

o

C to 125oC

Logic ICs

- 2V to 6V Operation

- High Noise Immunity: N
at VCC = 5V

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,
V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

OH

Pinout

CD54HC221

(CERDIP)

CD74HC221

(PDIP, SOIC, SOP, TSSOP)

CD74HCT221

(PDIP, SOIC)

TOP VIEW

16

V

CC

15

1C

XRX

14

1C

X

13

1Q

12

2Q

11

2R

10

2B

9

2A

2C

1A
1B
1R
1Q
2Q

2C

XRX

GND

1
2
3
4
5
6

X

7
8

Description

The ’HC221 and CD74HCT221 are dual monostable
multivibrators with reset. An external resistor (R
external capacitor (C
for the circuit. Adjustment of R
range of output pulse widths from the Q and
Pulse triggering on the B input occurs at a particular voltage
level and is not related to the rise and fall time of the trigger
pulse.

Once triggered, the outputs are independent of further trigger
inputs on
LOW level on the Reset (
and leading-edge-triggering (B) inputs are provided for
triggering from either edge of the input pulse. On power up,
the IC is reset. If either Mono is not used each input (on the
unused device) must be terminated either high or low.

The minimum value of external resistance, R
The minimum value of external capacitance, C
calculation for the pulse width is t

CC

Ordering Information

CD54HC221F3A -55 to 125 16 Ld CERDIP
CD74HC221E -55 to 125 16 Ld PDIP
CD74HC221M -55 to 125 16 Ld SOIC
CD74HC221MT -55 to 125 16 Ld SOIC
CD74HC221M96 -55 to 125 16 Ld SOIC
CD74HC221NSR -55 to 125 16 Ld SOP
CD74HC221PW -55 to 125 16 Ld TSSOP
CD74HC221PWR -55 to 125 16 Ld TSSOP
CD74HC221PWT -55 to 125 16 Ld TSSOP
CD74HCT221E -55 to 125 16 Ld PDIP
CD74HCT221M -55 to 125 16 Ld SOIC
CD74HCT221MT -55 to 125 16 Ld SOIC
CD74HCT221M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.

A and B. The output pulse can be terminated by a

PART NUMBER TEMP. RANGE (oC) PACKAGE

) control the timing and the accuracy

X

R) pin. Trailing Edge triggering (A)

and CXprovides a wide

X

X

= 0.7 RXCX at VCC = 4.5V.

W

) and an

X

Q terminals.

, is typically 500Ω.

, is 0pF. The

X

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

1

Functional Diagram

CD54HC221, CD74HC221, CD74HCT221

1A

1B

1R

2R

2A

2B

14 15

1C

X

1

2

3

11

9

10

2C

X

67

1CX1R

MONO 1

MONO 2

2CX2R

1CXR

2CXR

X

V

CC

X

13

1Q

4

1Q

5

2Q

12

2Q

X

V

CC

X

TRUTH TABLE

INPUTS OUTPUTS

ABRQQ

HXHLH
XLHLH

L ↑ H

↓

HH

XXLLH

LH↑

(Note 3) (Note 3)

H = High Voltage Level, L = Low Voltage Level, X = Irrelevant, ↑ = Transition from
Low to High Level,↓ = Transition from High to Low Level, = One High Level
Pulse, = One Low Level Pulse
NOTE:

1. For this combination the reset input must be low and the following sequence
must be used: pin 1 (or 9) must be set high or pin 2 (or 10) set low; then pin 1
(or 9) must be low and pin 2 (or 10) set high. Now the reset input goes from low­to-high and the device will be triggered.

2

Logic Diagram

V

1 (9)A2 (10)

S

QM QM

MASK

FF

CD54HC221, CD74HC221, CD74HCT221

B

R

S

QQ

4 (12) (13) 5

QQ

3 (11)

CC

N

16

15 (7)

RXC

14 (6)

C

8

R

X

C

X

GND

X

X

C

N

R

R

MAIN

FF

R1

RESET

V

CC

N

FF

PP

P

MIRROR VOLTAGE

PULLDOWN

V

CC

C
C

R

D
C

QC

FF

QD

Q

R

V

CC

OP

AMP

R4

P

-

+

P

R2

R3

+

­OP AMP

3

CD54HC221, CD74HC221, CD74HCT221

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time, tr, tf on Inputs A and R

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Input Rise and Fall Time, tr, tf on Input B

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

2. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Package Thermal Impedance, θJA(see Note 2):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64oC/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

V

IH

V

IL

V

OH

V

OL

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oC TO 125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

4

CD54HC221, CD74HC221, CD74HCT221

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Input Leakage

I

I

Current
Quiescent Device

I

CC

Current

HCT TYPES

High Level Input
Voltage

Low Level Input

V

IH

V

IL

Voltage
High Level Output

Voltage

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output
Voltage

V

OL

CMOS Loads
Low Level Output

Voltage
TTL Loads

Input Leakage

I

I

Current
Quiescent Device

Current
Additional Quiescent

Device Current Per

I

CC

∆I

CC

(Note 3)

Input Pin: 1 Unit Load

NOTE:

3. For dual-supply systems theoretical worst case (V

HCT Input Loading Table

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC or

GND

VCC or

GND

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

VCCand

GND

VCC or

GND

V

CC

-2.1

o

C -40oC TO 85oC -55oC TO 125oC

V

CC

(V)

25

UNITSV

-6--±0.1 - ±1-±1 µA

0 6 - - 8 - 80 - 160 µA

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

-4 4.5 3.98 - - 3.84 - 3.7 - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

INPUT UNIT LOADS

All Inputs 0.3

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table, e.g.,
360µA max at 25oC.

Prerequisite For Switching Function

PARAMETER SYMBOL VCC (V)

HC TYPES

Input Pulse Width

A

Input Pulse Width

B

t

t

WH

WL

270- -90-105-ns

4.5 14 - - 18 - 21 - ns
612- -15-18-ns
270- -90-105-ns

4.5 14 - - 18 - 21 - ns
612- -15-18-ns

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

5

CD54HC221, CD74HC221, CD74HCT221

Prerequisite For Switching Function (Continued)

PARAMETER SYMBOL VCC (V)

Input Pulse Width

Reset

Recovery Time
R to A or B

Output Pulse Width Q or Q
CX = 0.1µF RX = 10kΩ

Output Pulse Width Q or Q
CX = 28pF, RX = 2kΩ

CX = 1000pF, RX = 2kΩ t
CX = 1000pF, RX = 10kΩ t

HCT TYPES

Input Pulse Width

A

Input Pulse Width

B

Input Pulse Width

Reset

Recovery Time
R to A or B

Output Pulse Width Q or Q
CX = 0.1µF RX = 10kΩ

Output Pulse Width Q or Q
CX = 28pF, RX = 2kΩ

CX = 1000pF, RX = 2kΩ t
CX = 1000pF, RX = 10kΩ t

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
Trigger A, B, R to Q

Propagation Delay,
Trigger A, B, R to Q

t

PLH

t

PHL

t

t

t

t

WH

t

t

WL

t

t

WL

WL

t

t

270- -90-105-ns

4.5 14 - - 18 - 21 - ns
612- -15-18-ns

SU

20--0-0-ns

4.50--0-0-ns
60--0-0-ns

W

W

W
W

5 630 - 770 602 798 595 805 µs

4.5-140-----ns

4.5-1.5-----µs

4.5-7-----µs

4.5 14 - - 18 - 21 - ns

4.5 14 - - 18 - 21 - ns

4.5 18 - - 23 - 27 - ns

SU

W

W

W
W

, tf = 6ns

r

4.50--0-0-ns

5 630 - 770 602 798 595 805 µs

4.5-140-----ns

4.5-1.5-----µs

4.5-7-----µs

TEST

CONDITIONS VCC(V)

CL= 50pF 2 - - 210 - 265 - 315 ns
CL= 50pF 4.5 - - 42 - 53 - 63 ns
CL= 50pF 6 - - 36 - 45 - 54 ns
CL= 15pF 5 - 18 - - - - - ns
CL= 50pF 2 - - 170 - 215 - 255 ns
CL= 50pF 4.5 - - 34 - 43 - 51 ns
CL= 50pF 6 - - 29 - 37 - 43 ns
CL= 15pF 5 - 14 - - - - - ns

25oC -40oC TO 85oC -55oC TO 125oC

25oC

-40oC TO
85oC

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

UNITSMIN TYP MAX MIN MAX MIN MAX

6

CD54HC221, CD74HC221, CD74HCT221

Switching Specifications Input t

, tf = 6ns (Continued)

r

TEST

PARAMETER SYMBOL

Propagation Delay,
R to Q

t

PLH

CONDITIONS VCC(V)

CL= 50pF 2 - - 160 - 200 - 240 ns

4.5 - - 32 - 40 - 48 ns
6 - - 27 - 34 - 41 ns

Propagation Delay,
R to Q

t

PHL

CL= 50pF 2 - - 180 - 225 - 270 ns

4.5 - - 36 - 45 - 54 ns
6 - - 31 - 38 - 46 ns

Output Transition Time t

TLH

, t

CL= 50pF 2 - - 75 - 95 - 110 ns

THL

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

Input Capacitance C
Pulse Width Match Between

Circuits in the Same Package

IN

- - - - 10 - 10 - 10 pF

- 4.5 to

- ±2- - - - - %

5.5

CX = 1000pF, RX = 10kΩ
Power Dissipation Capacitance

CPD - 5 - 166 - - - - - pF

(Notes 4, 5)

HCT TYPES

Propagation Delay,
Trigger A, B, R to Q

Propagation Delay,
Trigger A, B, R to Q

Propagation Delay,

t

PLH

t

PHL

t

PLH

CL= 50pF 4.5 - - 42 - - - 63 ns
CL= 15pF 5 - 18 - - - - - ns
CL= 50pF 4.5 - - 34 - 43 - 51 ns
CL= 15pF 5 - 14 - - - - - ns
CL= 50pF 4.5 - - 38 - - - 57 ns

R to Q
Propagation Delay,

t

PHL

CL= 50pF 4.5 - - 37 - - - 56 ns

R to Q
Output Transition Time t

TLH

, t

CL= 50pF 2 - - 75 - 95 - 110 ns

THL

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

Input Capacitance C
Pulse Width Match Between

Circuits in the Same Package

IN

- - - - 10 - 10 - 10 pF

- 4.5 to

- ±2- - - - - %

5.5

CX = 1000pF, RX = 10kΩ
Power Dissipation Capacitance

CPD - 5 - 166 - - - - - pF

(Notes 4, 5)

NOTES:

4. CPD is used to determine the dynamic power consumption, per multivibrator.

5. PD = (CPD + CL) V

2

fi + Σ where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.

CC

25oC

-40oC TO
85oC

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

7

I

CD54HC221, CD74HC221, CD74HCT221

Test Circuits and Waveforms

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

L

WL

tWL+ tWH=

50%

t

WH

fC

50%

+ tWH=

t

t

WH

WL

1.3V

fC

L

3V

GND

I

L

V

CC

GND

trCL= 6ns

CLOCK

0.3V

2.7V

1.3V

0.3V

t

t

fCL

WL

= 6ns

1.3V

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

FIGURE 3. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

= 6ns

t

PLH

t

f

10%

1.3V

90%

t

TLH

3V

GND

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

2.7V

1.3V

0.3V

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

8

0

CD54HC221, CD74HC221, CD74HCT221

Typical Performance Curves

685

RX = 10K
VCC = 5V

680

675

, PULSE WIDTH (µs)

W

t

670

CX = 1µF

K FACTOR

0.9

0.8

0.7

RX = 10K

= 25oC

T

A

HCT

665

-75 -50 -25 0 25 50 75 100 125 150 175
, AMBIENT TEMPERATURE (oC)

T

A

FIGURE 5. HC/HCT221 OUTPUT PULSE WIDTH vs

TEMPERATURE

6

10

VCC = 2V

5

10

4

10

3

10

RX = 100K

2

10

, PULSE WIDTH (µs)

10

W

t

0.1

R

= 50K

X

= 10K

R

X

= 2K

R

1

X

2

10

10

3

10

10410

5

6

10

CX, TIMING CAPACITANCE (pF)

FIGURE 7. HC221 OUTPUT PULSE WIDTH vs C

10710

X

0.6
024681

VCC, SUPPLY VOLTAGE (V)

FIGURE 6. HC/HCT221 K FACTOR vs SUPPLY VOLTAGE

6

10

VCC = 4.5V

5

10

4

10

3

10

RX = 100K

2

10

, PULSE WIDTH (µs)

10

W

t

1

8

0.1

FIGURE 8. HC/HCT221 OUTPUT PULSE WIDTH vs C

= 50K

R

X

= 10K

R

X

= 2K

R

X

2

3

10

10

10

10410

5

10610710

8

CX, TIMING CAPACITANCE (pF)

X

9

CD54HC221, CD74HC221, CD74HCT221

10

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

5962-8780501EA ACTIVE CDIP J 16 1 Non-RoHS

CD54HC221F ACTIVE CDIP J 16 1 Non-RoHS

CD54HC221F3A ACTIVE CDIP J 16 1 Non-RoHS

CD74HC221E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC221E

CD74HC221M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC221M

CD74HC221M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC221M

CD74HC221M96E4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC221M

CD74HC221MG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC221M

CD74HC221MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC221M

CD74HC221NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC221M

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& Green

& Green

& Green

Lead finish/
Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

SNPB N / A for Pkg Type -55 to 125 5962-8780501EA

SNPB N / A for Pkg Type -55 to 125 CD54HC221F

SNPB N / A for Pkg Type -55 to 125 5962-8780501EA

21-Jan-2021

Samples

(4/5)

CD54HC221F3A

CD54HC221F3A

CD74HC221PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ221

CD74HC221PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ221

CD74HC221PWRE4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ221

CD74HC221PWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ221

CD74HCT221E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT221E

CD74HCT221EE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT221E

CD74HCT221M ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT221M

CD74HCT221M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT221M

CD74HCT221M96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT221M

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

CD74HCT221MG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT221M

CD74HCT221MT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT221M

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/
Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

21-Jan-2021

(4/5)

(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC221, CD74HC221 :

Samples

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

Catalog: CD74HC221

•

Military: CD54HC221

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Military - QML certified for Military and Defense Applications

•

21-Jan-2021

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com 17-Dec-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

CD74HC221M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

CD74HC221NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HC221PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC221PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

CD74HCT221M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Package
Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 17-Dec-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74HC221M96 SOIC D 16 2500 333.2 345.9 28.6

CD74HC221NSR SO NS 16 2000 853.0 449.0 35.0
CD74HC221PWR TSSOP PW 16 2000 853.0 449.0 35.0
CD74HC221PWT TSSOP PW 16 250 853.0 449.0 35.0

CD74HCT221M96 SOIC D 16 2500 333.2 345.9 28.6

Pack Materials-Page 2

PACKAGE OUTLINE

A

5.1

4.9

NOTE 3

SCALE 2.500

TSSOP - 1.2 mm max heightPW0016A

SMALL OUTLINE PACKAGE

SEATING

6.6

TYP

6.2
PIN 1 INDEX AREA

1

8

B

4.5

4.3

NOTE 4

16

9

14X 0.65

2X

4.55

0.30

16X

0.19

0.1 C A B

C

1.2 MAX

PLANE

0.1 C

(0.15) TYP

SEE DETAIL A

GAGE PLANE

0.25

0.75

-80

0.50

A 20

DETAIL A

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

0.15

0.05

www.ti.com

EXAMPLE BOARD LAYOUT

TSSOP - 1.2 mm max heightPW0016A

SMALL OUTLINE PACKAGE

16X (0.45)

14X (0.65)

1

8

16X (1.5)

SYMM

(R0.05) TYP

16

SYMM

9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SOLDER MASK

OPENING

EXPOSED METAL

0.05 MAX
ALL AROUND

NON-SOLDER MASK

DEFINED

(PREFERRED)

METAL

SOLDER MASK DETAILS

15.000

METAL UNDER
SOLDER MASK

0.05 MIN
ALL AROUND

SOLDER MASK

DEFINED

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SOLDER MASK
OPENING

EXPOSED METAL

4220204/A 02/2017

www.ti.com

EXAMPLE STENCIL DESIGN

TSSOP - 1.2 mm max heightPW0016A

SMALL OUTLINE PACKAGE

16X (0.45)

14X (0.65)

1

8

16X (1.5)

SYMM

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

(R0.05) TYP

16

SYMM

9

4220204/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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