Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT21
Dual 4-input AND gate
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
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December 1990 2
Philips Semiconductors Product specification
Dual 4-input AND gate 74HC/HCT21
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT21 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT21 provide the 4-input AND function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi + ∑ (CL× V
CC
2
× fO) where:
fi= input frequency in MHz
fo= output frequency in MHz
CL= output load capacitance in pF
VCC= supply voltage in V
∑ (CL× V
CC
2
× fo) = sum of outputs
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay nA, nB, nC, nD to nY CL= 15 pF; VCC= 5 V 10 12 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per package notes 1 and 2 15 16 pF
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December 1990 3
Philips Semiconductors Product specification
Dual 4-input AND gate 74HC/HCT21
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 9 1A, 2A data inputs
2, 10 1B, 2B data inputs
3, 11 n.c. not connected
4, 12 1C, 2C data inputs
5, 13 1D, 2D data inputs
6, 8 1Y, 2Y data outputs
7 GND ground (0 V)
14 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
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December 1990 4
Philips Semiconductors Product specification
Dual 4-input AND gate 74HC/HCT21
Fig.4 Functional diagram. Fig.5 Logic diagram (one gate).
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
INPUTS OUTPUT
nA nB nC nD nY
LXXX L
XLXX L
X XLX L
XXXL L
HHHH H
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December 1990 5
Philips Semiconductors Product specification
Dual 4-input AND gate 74HC/HCT21
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C) TEST CONDITIONS
74HC
UNIT
V
CC
(V)
WAVEFORMS
+25 −40 to+85 −40 to+125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nA, nB, nC, nD to nY
33 110 140 165 ns 2.0 Fig.6
12 22 28 33 4.5
10 19 24 28 6.0
t
THL
/ t
TLH
output transition time 19 75 95 110 ns 2.0 Fig.6
7 15 19 22 4.5
6 13 16 19 6.0
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December 1990 6
Philips Semiconductors Product specification
Dual 4-input AND gate 74HC/HCT21
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: SSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
INPUT UNIT LOAD COEFFICIENT
nA, nB, 1.50
nC, nD 1.50
SYMBOL PARAMETER
T
amb
(°C) TEST CONDITIONS
74HCT
UNIT
V
CC
(V)
WAVEFORMS
+25 −40 to+85 −40 to+125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nA, nB nC, nD to nY
15 27 34 41 ns 4.5 Fig.6
t
THL
/ t
TLH
output transition time 7 15 19 22 ns 4.5 Fig.6
Fig.6 Waveforms showing the input (nA, nB, nC, nD) to output (nY) propagation delays and the output transition
times.
(1) HC: VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
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