Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT194
4-bit bidirectional universal shift
register
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
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December 1990 2
Philips Semiconductors Product specification
4-bit bidirectional universal shift register 74HC/HCT194
FEATURES
• Shift-left and shift-right capability
• Synchronous parallel and serial data transfer
• Easily expanded for both serial and parallel operation
• Asynchronous master reset
• Hold (“do nothing”) mode
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT194 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The functional characteristics of the 74HC/HCT194 4-bit
bidirectional universal shift registers are indicated in the
logic diagram and function table. The registers are fully
synchronous.
The “194” design has special features which increase the
range of application. The synchronous operation of the
device is determined by the mode select inputs (S
0
, S1).
As shown in the mode select table, data can be entered
and shifted from left to right (Q0→ Q1→ Q2, etc.) or, right
to left (Q3→ Q2→ Q1, etc.) or parallel data can be
entered, loading all 4 bits of the register simultaneously.
When both S0 and S1 are LOW, existing data is retained in
a hold (“do nothing”) mode. The first and last stages
provide D-type serial data inputs (DSR, DSL) to allow
multistage shift right or shift left data transfers without
interfering with parallel load operation.
Mode select and data inputs are edge-triggered,
responding only to the LOW-to-HIGH transition of the
clock (CP). Therefore, the only timing restriction is that the
mode control and selected data inputs must be stable one
set-up time prior to the positive transition of the clock
pulse.
The four parallel data inputs (D0 to D3) are D-type inputs.
Data appearing on the D0 to D3 inputs, when S0 and S1 are
HIGH, is transferred to the Q0 to Q3 outputs respectively,
following the next LOW-to-HIGH transition of the clock.
When LOW, the asynchronous master reset (MR)
overrides all other input conditions and forces the Q
outputs LOW.
The “194” is similar in operation to the “195” universal shift
register, with added features of shift-left without external
connections and hold (“do nothing”) modes of operation.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi+∑(CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ =(CL×V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to VCC; for HCT the condition is VI= GND to VCC− 1.5 V
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay CL= 15 pF; VCC=5 V
CP to Q
n
14 15 ns
t
PHL
MR to Q
n
11 15 ns
f
max
maximum clock frequency 102 77 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per package notes 1 and 2 40 40 pF
Page 3
December 1990 3
Philips Semiconductors Product specification
4-bit bidirectional universal shift register 74HC/HCT194
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
MR asynchronous master reset input (active LOW)
2D
SR
serial data input (shift right)
3, 4, 5, 6 D
0
to D
3
parallel data inputs
7D
SL
serial data input (shift left)
8 GND ground (0 V)
9, 10 S
0
, S
1
mode control inputs
11 CP clock input (LOW-to-HIGH edge-triggered)
15, 14, 13, 12 Q
0
to Q
3
parallel outputs
16 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
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December 1990 4
Philips Semiconductors Product specification
4-bit bidirectional universal shift register 74HC/HCT194
FUNCTION TABLE
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q,d = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the
LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition
OPERATING MODES
INPUTS OUTPUTS
CP MR S
1
S
0
D
SR
D
SL
D
n
Q
0
Q
1
Q
2
Q
3
reset (clear) X L XXXXXLLLL
hold (“do nothing”) X H I I X X X q
0
q
1
q
2
q
3
shift left
↑
↑
H
H
h
h
I
I
X
X
I
h
X
X
q
1
q
1
q
2
q
2
q
3
q
3
L
H
shift right
↑
↑
H
H
I
I
h
h
I
h
X
X
X
X
L
H
q
0
q
0
q
1
q
1
q
2
q
2
parallel load ↑ HhhXXd
n
d
0
d
1
d
2
d
3
Fig.4 Functional diagram.
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December 1990 5
Philips Semiconductors Product specification
4-bit bidirectional universal shift register 74HC/HCT194
Fig.5 Logic diagram.
Fig.6 Typical clear, clear-load, shift-right, shift-left, inhibit and clear timing sequences.
Page 6
December 1990 6
Philips Semiconductors Product specification
4-bit bidirectional universal shift register 74HC/HCT194
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Page 7
December 1990 7
Philips Semiconductors Product specification
4-bit bidirectional universal shift register 74HC/HCT194
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
47
17
14
145
29
25
180
36
31
220
44
38
ns 2.0
4.5
6.0
Fig.7
t
PHL
propagation delay
MR to Q
n
39
14
11
140
28
24
175
35
30
210
42
36
ns 2.0
4.5
6.0
Fig.8
t
THL
/ t
TLH
output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.7
t
W
clock pulse width
HIGH or LOW
80
16
14
17
6
5
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.7
t
W
master reset pulse
width; LOW
80
16
14
17
6
5
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.8
t
rem
removal time
MR to CP
60
12
10
17
6
5
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.8
t
su
set-up time
Dn to CP
70
14
12
17
6
5
90
18
15
105
21
18
ns 2.0
4.5
6.0
Fig.9
t
su
set-up time
S0, S1 to CP
80
16
12
22
8
6
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.10
t
su
set-up time
DSR, DSL to CP
70
14
12
19
7
6
90
18
15
105
21
18
ns 2.0
4.5
6.0
t
h
hold time
Dn to CP
0
0
0
−14
−5
−4
0
0
0
0
0
0
ns 2.0
4.5
6.0
Fig.9
t
h
hold time
S0, S1to CP
0
0
0
−11
−4
−3
0
0
0
0
0
0
ns 2.0
4.5
6.0
Fig.10
t
h
hold time
DSR, DSL to CP
0
0
0
−17
−6
−5
0
0
0
0
0
0
ns 2.0
4.5
6.0
f
max
maximum clock pulse
frequency
6.0
30
35
31
93
111
4.8
24
28
4.0
20
24
MHz 2.0
4.5
6.0
Fig.7
Page 8
December 1990 8
Philips Semiconductors Product specification
4-bit bidirectional universal shift register 74HC/HCT194
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
D
n
DSR, D
SL
CP
MR
S
n
0.15
0.15
0.50
0.45
0.90
Page 9
December 1990 9
Philips Semiconductors Product specification
4-bit bidirectional universal shift register 74HC/HCT194
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
18 32 40 48 ns 4.5 Fig.7
t
PHL
propagation delay
MR to Q
n
18 32 40 48 ns 4.5 Fig.8
t
THL
/ t
TLH
output transition time 7 15 19 22 ns 4.5 Fig.7
t
W
clock pulse width
HIGH or LOW
16 7 20 24 ns 4.5 Fig.7
t
W
master reset pulse
width; LOW
16 7 20 24 ns 4.5 Fig.8
t
rem
removal time
MR to CP
12 6 15 18 ns 4.5 Fig.8
t
su
set-up time
Dn to CP
14 7 18 21 ns 4.5 Fig.9
t
su
set-up time
S0, S1 to CP
20 10 25 30 ns 4.5 Fig.10
t
su
set-up time
DSR, DSL to CP
14 18 21 ns 4.5 Fig.9
t
h
hold time
Dn to CP
0 −7 0 0 ns 4.5 Fig.9
t
h
hold time
S0, S1to CP
0 −5 0 0 ns 4.5 Fig.10
t
h
hold time
DSR, DSL to CP
0 −7 0 0 ns 4.5 Fig.9
f
max
maximum clock pulse
frequency
30 70 24 20 MHz 4.5 Fig.7
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December 1990 10
Philips Semiconductors Product specification
4-bit bidirectional universal shift register 74HC/HCT194
AC WAVEFORMS
Fig.7 Waveforms showing the clock (CP) to
output (Qn) propagation delays, the clock
pulse width, the output transition times and
the maximum clock frequency.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.8 Waveforms showing the master reset (MR)
pulse width, the master reset to output (Qn)
propagation delays and the master reset to
clock (CP) removal time.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.9 Waveforms showing the set-up and hold
times from the data inputs (Dn, DSR and
DSL) to the clock (CP).
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
M
= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.10 Waveforms showing the set-up and hold
times from the mode control inputs (Sn) to
the clock input (CP).
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
M
= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
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