Datasheet 74HC 175 Datasheet (FREI)

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Page 1

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT175

Quad D-type flip-flop with reset; positive-edge trigger

Product speciﬁcation Supersedes data of December 1990 File under Integrated Circuits, IC06

1998 Jul 08

Page 2

Philips Semiconductors Product speciﬁcation

Quad D-type ﬂip-ﬂop with reset; positive-edge trigger 74HC/HCT175

FEATURES

• Four edge-triggered D flip-flops

• Output capability: standard

• ICC category: MSI

The 74HC/HCT175 have four edge-triggered, D-type flip-flops with individual D inputs and both Q and outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the

GENERAL DESCRIPTION

The 74HC/HCT175 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL

corresponding output (Qn) of the flip-flop. All Qn outputs will be forced LOW independently of clock

or data inputs by a LOW voltage level on the MR input.

(LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The device is useful for applications where both the true and complement outputs are required and the clock and master reset are common to all storage elements.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

PHL

PLH

max

C C

I PD

propagation delay CL= 15 pF; VCC=5 V

CP to Q MR to Q

, Q

propagation delay

CP to Q MR to Q

, Q

maximum clock frequency 83 54 MHz input capacitance 3.5 3.5 pF power dissipation capacitance per flip-flop notes 1 and 2 32 34 pF

TYPICAL

UNIT

HC HCT

17 16 ns 15 19 ns

17 16 ns 15 16 ns

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD=CPD× V

× fi+ ∑ (CL× V

× fo) where:

fi= input frequency in MHz fo= output frequency in MHz ∑ (CL× V

× fo) = sum of outputs

CL= output load capacitance in pF VCC= supply voltage in V

2. For HC the condition is VI= GND to V

For HCT the condition is VI= GND to VCC− 1.5 V

1998 Jul 08 2

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Philips Semiconductors Product speciﬁcation

Quad D-type ﬂip-ﬂop with reset; positive-edge trigger 74HC/HCT175

ORDERING INFORMATION

TYPE

NUMBER

74HC175N;

NAME DESCRIPTION VERSION

DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1

PACKAGE

74HCT175N 74HC175D;

SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

74HCT175D 74HC175DB;

SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

74HCT175DB 74HC175PW;

TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

74HCT175PW

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 2, 7, 10, 15 Q 3, 6, 11, 14 4, 5, 12, 13 D

MR master reset input (active LOW)

to Q

Q0 to Q

to D

3 3

ﬂip-ﬂop outputs complementary ﬂip-ﬂop outputs

data inputs 8 GND ground (0 V) 9 CP clock input (LOW-to-HIGH, edge-triggered) 16 V

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

1998 Jul 08 3

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Philips Semiconductors Product speciﬁcation

Quad D-type ﬂip-ﬂop with reset; positive-edge trigger 74HC/HCT175

Fig.4 Functional diagram.

FUNCTION TABLE

OPERATING MODES

INPUTS OUTPUTS

MR CP D

reset (clear) L X X L H load “1” H ↑ hH L load “0” H ↑ ILH

Note

1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition ↑ = LOW-to-HIGH CP transition X = don’t care

Fig.5 Logic diagram.

1998 Jul 08 4

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Philips Semiconductors Product speciﬁcation

Quad D-type ﬂip-ﬂop with reset; positive-edge trigger 74HC/HCT175

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: standard ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL PARAMETER

PHL

THL

/ t

propagation delay

PLH

CP to Qn, Q

propagation delay

PLH

MR to Qn, Q

output transition time 19 75 95 110 ns 2.0 Fig.6

TLH

clock pulse width

HIGH or LOW

master reset pulse width

LOW

rem

removal time

MR to CP

set-up time

Dn to CP

max

hold time

CP to D

maximum clock pulse

frequency

amb

(°C)

TEST CONDITIONS

74HC

+25 −40 to +85 −40 to +125

UNIT

WAVEFORMS

(V)

min. typ. max. min. max. min. max.

55 175 220 265 ns 2.0 Fig.6 20 35 44 53 4.5 16 30 37 45 6.0 50 150 190 225 ns 2.0 Fig.8 18 30 38 45 4.5 14 26 33 38 6.0

7 15 19 22 4.5

6 13 16 19 6.0 80 22 100 120 ns 2.0 Fig.6 16 8 20 24 4.5 14 6 17 20 6.0 80 19 100 120 ns 2.0 Fig.8 16 7 20 24 4.5 14 6 17 20 6.0 5 −33 5 5 ns 2.0 Fig.8 5 −12 5 5 4.5 5 −10 5 5 6.0 80 3 100 120 ns 2.0 Fig.7 16 1 20 24 4.5 14 1 17 20 6.0 25 2 30 40 ns 2.0 Fig.7 5 0 6 8 4.5 4 0 5 7 6.0

6.0 25 4.8 4.0 MHz 2.0 Fig.6 30 75 24 20 4.5 35 89 28 24 6.0

1998 Jul 08 5

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Philips Semiconductors Product speciﬁcation

Quad D-type ﬂip-ﬂop with reset; positive-edge trigger 74HC/HCT175

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: standard ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆I

) for a unit load of 1 is given in the family specifications.

To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

MR 1.00 CP 0.60 D

0.40

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; tr=tf= 6 ns; CL= 50 pF

amb

(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

+25 −40 to +85 −40 to +125

UNIT

(V)

min. typ. max. min. max. min. max.

PHL

PLH

THL

/ t

propagation delay

PLH

CP to Qn, Q

propagation delay

MR to Q

propagation delay

MR to Q

output transition time 7 15 19 22 ns 4.5 Fig.6

TLH

19 33 41 50 ns 4.5 Fig.6

22 38 48 57 ns 4.5 Fig.8

19 35 44 53 ns 4.5 Fig.8

WAVEFORMS

clock pulse width

20 12 25 30 ns 4.5 Fig.6

HIGH or LOW

master reset pulse width

20 11 25 30 ns 4.5 Fig.8

LOW

rem

removal time

5 −10 5 5 ns 4.5 Fig.8

MR to CP

set-up time

16 5 20 24 ns 4.5 Fig.7

Dn to CP

max

hold time

CP to D

maximum clock pulse

5 0 5 5 ns 4.5 Fig.7

25 49 20 17 MHz 4.5 Fig.6

frequency

1998 Jul 08 6

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Philips Semiconductors Product speciﬁcation

Quad D-type ﬂip-ﬂop with reset; positive-edge trigger 74HC/HCT175

AC WAVEFORMS

(1) HC : VM= 50%; VI= GND to VCC.

HCT : V

= 1.3 V; VI= GND to 3 V.

Fig.6 Waveforms showing the clock (CP) to

outputs (Qn, Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency.

The shaded areas indicate when the input is permitted to change for predictable output performance.

(1) HC : VM= 50%; VI= GND to VCC.

HCT : V

= 1.3 V; VI= GND to 3 V.

Fig.7 Waveforms showing the data set-up and

hold times for the data input (Dn).

(1) HC : VM= 50%; VI= GND to VCC.

HCT : V

= 1.3 V; VI= GND to 3 V.

Fig.8 Waveforms showing the master reset (MR)

pulse width, the master reset to outputs (Qn, Qn) propagation delays and the master reset to clock (CP) removal time.

1998 Jul 08 7

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Philips Semiconductors Product speciﬁcation

Quad D-type ﬂip-ﬂop with reset; positive-edge trigger 74HC/HCT175

PACKAGE OUTLINES

DIP16: plastic dual in-line package; 16 leads (300 mil); long body

seating plane

pin 1 index

w M

SOT38-1

(e )

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

4.7 0.51 3.7

OUTLINE

VERSION

SOT38-1

min.

1 2

max.

0.15

IEC JEDEC EIAJ

050G09 MO-001AE

1.40

1.14

0.055

0.045

0.53

0.38

0.021

0.015

cEe M

0.32

0.23

0.013

0.009

REFERENCES

(1) (1)

21.8

21.4

0.86

0.84

1998 Jul 08 8

6.48

6.20

0.26

0.24

0.30

0.15

0.13

3.9

3.4

8.25

7.80

0.32

0.31

EUROPEAN

PROJECTION

9.5

0.2542.54 7.62

8.3

0.37

0.010.100.0200.19

0.33

ISSUE DATE

92-10-02 95-01-19

max.

2.2

0.087

(1)

Page 9

Philips Semiconductors Product speciﬁcation

Quad D-type ﬂip-ﬂop with reset; positive-edge trigger 74HC/HCT175

SO16: plastic small outline package; 16 leads; body width 3.9 mm

pin 1 index

w M

SOT109-1

detail X

v M

(A )

0 2.5 5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

OUTLINE

VERSION

SOT109-1

max.

1.75

0.069

A1A2A

0.25

1.45

0.10

1.25

0.010

0.057

0.004

0.049

0.25

0.01

IEC JEDEC EIAJ

076E07S MS-012AC

0.49

0.36

0.019

0.014

0.25

0.19

0.0100

0.0075

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1) (1)

10.0

4.0

9.8

3.8

0.39

0.16

0.15

0.050

0.38

REFERENCES

1998 Jul 08 9

eHELLpQZywv θ

1.27

6.2

5.8

0.244

0.228

1.05

0.041

1.0

0.4

0.039

0.016

0.7

0.25

0.6

0.028

0.01 0.004

0.020

EUROPEAN

PROJECTION

0.25 0.1

0.01

0.7

0.3

0.028

0.012

ISSUE DATE

95-01-23 97-05-22

Page 10

Philips Semiconductors Product speciﬁcation

Quad D-type ﬂip-ﬂop with reset; positive-edge trigger 74HC/HCT175

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

pin 1 index

SOT338-1

v M

(A )

DIMENSIONS (mm are the original dimensions)

OUTLINE VERSION

SOT338-1

max.

2.0

0.21

0.05

1.80

1.65

IEC JEDEC EIAJ

0.25

0.38

0.25

UNIT A1A2A

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.20

0.09

REFERENCES

MO-150AC

w M

0 2.5 5 mm

scale

(1)E(1)

6.4

5.4

6.0

0.65 1.25

5.2

1998 Jul 08 10

detail X

eHELLpQZywv θ

7.9

7.6

1.03

0.63

0.9

0.7

EUROPEAN

PROJECTION

0.130.2 0.1

(1)

1.00

0.55

ISSUE DATE

94-01-14 95-02-04

Page 11

Philips Semiconductors Product speciﬁcation

Quad D-type ﬂip-ﬂop with reset; positive-edge trigger 74HC/HCT175

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

pin 1 index

w M

detail X

SOT403-1

v M

(A )

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

max.

0.15

1.10

OUTLINE VERSION

SOT403-1 MO-153

0.05

0.95

0.80

IEC JEDEC EIAJ

0.25

0.30

0.19

0.2

0.1

(1)E(2) (1)

5.1

4.5

4.3

0.65

4.9

REFERENCES

1998 Jul 08 11

eHELLpQZywv θ

6.6

6.2

0.75

0.50

0.4

0.3

EUROPEAN

PROJECTION

0.13 0.10.21.0

0.40

0.06

ISSUE DATE

94-07-12 95-04-04

Page 12

Philips Semiconductors Product speciﬁcation

Quad D-type ﬂip-ﬂop with reset; positive-edge trigger 74HC/HCT175

SOLDERING Introduction

There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our

“Data Handbook IC26; Integrated Circuit Packages”

(order code 9398 652 90011).

DIP

OLDERING BY DIPPING OR BY WAVE

The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T

stg max

). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.

SO, SSOP and TSSOP

REFLOW SOLDERING Reflow soldering techniques are suitable for all SO, SSOP

and TSSOP packages. Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method.

Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.

AVE SOLDERING

W Wave soldering can be used for all SO packages. Wave

soldering is not recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.

If wave soldering is used - and cannot be avoided for SSOP and TSSOP packages - the following conditions must be observed:

• A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.

• The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end.

Even with these conditions:

• Only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1).

• Do not consider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP56 (SOT364-1).

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

1998 Jul 08 12

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Philips Semiconductors Product speciﬁcation

Quad D-type ﬂip-ﬂop with reset; positive-edge trigger 74HC/HCT175

REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less

than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

DEFINITIONS

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

1998 Jul 08 13