Page 1
DATA SH EET
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Jul 08
INTEGRATED CIRCUITS
74HC/HCT174
Hex D-type flip-flop with reset;
positive-edge trigger
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
Page 2
1998 Jul 08 2
Philips Semiconductors Product specification
Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174
FEATURES
• Six edge-triggered D-type flip-flops
• Asynchronous master reset
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT174 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT174 have six edge-triggered D-type
flip-flops with individual D inputs and Q outputs. The
common clock (CP) and master reset (
MR) inputs load and
reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time prior to the LOW-to-HIGH clock
transition, is transferred to the corresponding output of the
flip-flop.
A LOW level on the MR input forces all outputs LOW,
independently of clock or data inputs.
The device is useful for applications requiring true outputs
only and clock and master reset inputs that are common to
all storage elements.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi+∑ (CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay CL= 15 pF; VCC=5 V
CP to Q
n
17 18 ns
MR to Q
n
13 17 ns
f
max
maximum clock frequency 99 69 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation
capacitance per flip-flop
notes 1 and 2 17 17 pF
Page 3
1998 Jul 08 3
Philips Semiconductors Product specification
Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174
ORDERING INFORMATION
PIN DESCRIPTION
TYPE
NUMBER
PACKAGE
NAME DESCRIPTION VERSION
74HC174N;
74HCT174N
DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
74HC174D;
74HCT174D
SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HC174DB;
74HCT174DB
SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
74HC174PW;
74HCT174PW
TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
PIN NO. SYMBOL NAME AND FUNCTION
1
MR asynchronous master reset (active LOW)
2, 5, 7, 10, 12, 15 Q
0
to Q
5
flip-flop outputs
3, 4, 6, 11, 13, 14 D
0
to D
5
data inputs
8 GND ground (0 V)
9 CP clock input (LOW-to-HIGH, edge-triggered)
16 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Fig.3 IEC logic symbol.
Page 4
1998 Jul 08 4
Philips Semiconductors Product specification
Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174
FUNCTION TABLE
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
X = don’t care
↑= LOW-to-HIGH CP transition
OPERATING MODES
INPUTS OUTPUTS
MR CP D
n
Q
n
reset (clear) L X X L
load “1” H ↑ hH
load “0” H ↑ IL
Fig.4 Functional diagram.
Fig.5 Logic diagram.
Page 5
1998 Jul 08 5
Philips Semiconductors Product specification
Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
55 165 205 250 ns 2.0 Fig.6
20 33 41 50 4.5
16 28 35 43 6.0
t
PHL
propagation delay
MR to Q
n
44 150 190 225 ns 2.0 Fig.7
16 30 38 45 4.5
13 26 33 38 6.0
t
THL
/ t
TLH
output transition time 19 75 95 110 ns 2.0 Fig.6
7 15 19 22 4.5
6 13 16 19 6.0
t
W
clock pulse width
HIGH or LOW
80 17 100 120 ns 2.0 Fig.6
16 6 20 24 4.5
14 5 17 20 6.0
t
W
master reset pulse
width; LOW
80 12 100 120 ns 2.0 Fig.7
16 4 20 24 4.5
14 3 17 20 6.0
t
rem
removal time
MR to CP
5 −11 5 5 ns 2.0 Fig.7
5 −4 5 5 4.5
5 −3 5 5 6.0
t
su
set-up time
Dn to CP
60 6 75 90 ns 2.0 Fig.8
12 2 15 18 4.5
10 2 13 15 6.0
t
h
hold time
Dn to CP
3 −6 3 3 ns 2.0 Fig.8
3 −2 3 3 4.5
3 −2 3 3 6.0
f
max
maximum clock pulse
frequency
6 30 5 4 MHz 2.0 Fig.6
30 90 24 20 4.5
35 107 28 24 6.0
Page 6
1998 Jul 08 6
Philips Semiconductors Product specification
Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=tf= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
D
n
0.25
CP 1.30
MR 1.25
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
21 35 44 53 ns 4.5 Fig.6
t
PHL
propagation delay
MR to Q
n
20 35 44 53 ns 4.5 Fig.7
t
THL
/ t
TLH
output transition time 7 15 19 22 ns 4.5 Fig.6
t
W
clock pulse width
HIGH or LOW
16 7 20 24 ns 4.5 Fig.6
t
W
master reset pulse
width; LOW
20 7 25 30 ns 4.5 Fig.7
t
rem
removal time MR to CP 12 −3 15 18 ns 4.5 Fig.7
t
su
set-up time Dn to CP 16 4 20 24 ns 4.5 Fig.8
t
h
hold time Dn to CP 5 −3 5 5 ns 4.5 Fig.8
f
max
maximum clock pulse
frequency
30 63 24 20 MHz 4.5 Fig.6
Page 7
1998 Jul 08 7
Philips Semiconductors Product specification
Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174
AC WAVEFORMS
Fig.6 Waveforms showing the clock (CP) to output
(Qn) propagation delays, the clock pulse
width, the output transition times and the
maximum clock pulses frequency.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
M
= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the master reset (MR)
pulse width, the master reset to output (Qn)
propagation delays and the master reset to
clock (CP) removal time.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
M
= 1.3 V; VI= GND to 3 V.
Fig.8 Waveforms showing the data set-up and hold times for the data input (Dn).
The shaded areas indicate when the input is permitted to
change for predictable output performance
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
M
= 1.3 V; VI= GND to 3 V.
Page 8
1998 Jul 08 8
Philips Semiconductors Product specification
Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174
PACKAGE OUTLINES
UNIT
A
max.
1 2
b
1
cEe M
H
L
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT38-1
92-10-02
95-01-19
A
min.
A
max.
b
max.
w
M
E
e
1
1.40
1.14
0.055
0.045
0.53
0.38
0.32
0.23
21.8
21.4
0.86
0.84
6.48
6.20
0.26
0.24
3.9
3.4
0.15
0.13
0.2542.54 7.62
0.30
8.25
7.80
0.32
0.31
9.5
8.3
0.37
0.33
2.2
0.087
4.7 0.51 3.7
0.15
0.021
0.015
0.013
0.009
0.010.100.0200.19
050G09 MO-001AE
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w M
b
1
e
D
A
2
Z
16
1
9
8
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
(1) (1)
D
(1)
Z
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
Page 9
1998 Jul 08 9
Philips Semiconductors Product specification
Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M
A
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT
A
max.
A1A2A
3
b
p
cD
(1)E(1) (1)
eHELLpQZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3
8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.0
0.4
SOT109-1
95-01-23
97-05-22
076E07S MS-012AC
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.39
0.38
0.16
0.15
0.050
1.05
0.041
0.244
0.228
0.028
0.020
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
Page 10
1998 Jul 08 10
Philips Semiconductors Product specification
Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174
UNIT A1A2A
3
b
p
cD
(1)E(1)
eHELLpQZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65 1.25
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1
94-01-14
95-02-04
(1)
w M
b
p
D
H
E
E
Z
e
c
v M
A
X
A
y
1
8
16
9
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
MO-150AC
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
A
max.
2.0
Page 11
1998 Jul 08 11
Philips Semiconductors Product specification
Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174
UNIT A1A
2
A
3
b
p
cD
(1)E(2) (1)
eHELLpQZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.40
0.06
8
0
o
o
0.13 0.10.21.0
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153
94-07-12
95-04-04
w M
b
p
D
Z
e
0.25
18
16
9
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M
A
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
A
max.
1.10
pin 1 index
Page 12
1998 Jul 08 12
Philips Semiconductors Product specification
Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
DIP
S
OLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
stg max
). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
R
EPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
SO, SSOP and TSSOP
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO, SSOP
and TSSOP packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method.
Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
W
AVE SOLDERING
Wave soldering can be used for all SO packages. Wave
soldering is not recommended for SSOP and TSSOP
packages, because of the likelihood of solder bridging due
to closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering is used - and cannot be avoided for
SSOP and TSSOP packages - the following conditions
must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder
thieves at the downstream end.
Even with these conditions:
• Only consider wave soldering SSOP packages that
have a body width of 4.4 mm, that is
SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
• Do not consider wave soldering TSSOP packages
with 48 leads or more, that is TSSOP48 (SOT362-1)
and TSSOP56 (SOT364-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Page 13
1998 Jul 08 13
Philips Semiconductors Product specification
Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less
than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a
dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
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