The M54/74HC174 is a high speed CMOSHEXDTYPE FLIP-FLOP WITH CLEAR fabricated in silicon gate C2MOStechnology. It has the same high
speed performance of LSTTL combined with true
CMOS low powerconsumption.
Information signals applied to D inputs are transfered to the Q outputon the positive goingedge of
the clock pulse. Whenthe CLEARinput isheld low,
the Q outputs are held low independently of the
other inputs. All inputs are equippedwith protection
circuits against static discharge and transient excess voltage.
M54HC174
M74HC174
B1R
(PlasticPackage)
M1R
(MicroPackage)
ORDER CODES :
M54HC 174F1RM74H C174M1R
M74HC 174B1RM74HC1 74C1R
PIN CONNECTIONS(top view)
F1R
(CeramicPackage)
C1R
(Chip Carrier)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
October 1992
NC =
No Internal
Connection
1/11
Page 2
M54/M74HC174
TRUTH TABLE
INPUTSOUTPUTS
CLEARDCKQ
LXXLCLEAR
HLL
HHH
HXQ
X:Don’tCare
PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1CLEARAsynchronous Master
Reset (Active LOW)
2, 5, 7, 10,
12, 15
3, 4, 6, 11,
13, 14
9CLOCKClock Input (LOW to
8GNDGround (0V)
16V
Q0 to Q5Flip-flop Outputs
D0 to D5Data Inputs
HIGH, edge triggered)
CC
Positive Supply Voltage
n
IEC LOGIC SYMBOL
FUNCTION
NO CHANGE
LOGI C DIAGRAM
2/11
Page 3
M54/M74HC174
ABSOLU TE M AXI MU M R AT INGS
SymbolParameterValueUnit
V
CC
V
V
O
I
IK
I
OK
I
O
I
or I
CC
P
D
T
stg
T
AbsoluteMaximumRatingsarethose values beyond whichdamage tothedevicemayoccur. Functional operation under these conditionisnotimplied.
(*)500 mW: ≅ 65oC derateto300mWby 10mW/oC: 65oCto85oC
RECO MM ENDED O PERAT IN G CONDITI ONS
SymbolParameterValueUnit
V
CC
V
I
V
O
T
op
t
r,tf
Supply Voltage-0.5 to +7V
DC Input Voltage-0.5 to VCC+ 0.5V
I
DC Output Voltage-0.5 to VCC+ 0.5V
DC Input Diode Current± 20mA
DC Output Diode Current± 20mA
DC Output Source Sink Current Per Output Pin± 25mA
DC VCCor Ground Current± 50mA
GND
Power Dissipation500 (*)mW
Storage Temperature-65 to +150
Lead Temperature (10 sec)300
L
Supply Voltage2 to 6V
Input Voltage0 to V
Output Voltage0 to V
Operating Temperature: M54HC Series
M74HC Series
CC
CC
-55 to +125
-40 to +85
Input Rise and Fall TimeVCC= 2 V0 to 1000ns
V
= 4.5 V0 to 500
CC
= 6 V0 to 400
V
CC
o
C
o
C
V
V
o
C
o
C
3/11
Page 4
M54/M74HC174
DC SPECIFICATIO NS
SymbolParameter
V
V
V
V
I
High Level Input
IH
Voltage
Low Level Input
IL
Voltage
High Level
OH
Output Voltage
Low Level Output
OL
Voltage
I
Input Leakage
I
Current
Quiescent Supply
CC
Current
Test ConditionsValue
V
(V)
CC
=25oC
A
54HC and 74HC
Min.Typ.Max.Min.Max.Min.Max.
-40 to 85oC
74HC
-55 to 125oC
54HC
Unit
T
2.01.51.51.5
4.53.153.153.15
6.04.24.24.2
2.00.50.50.5
4.51.351.351.35
6.01.81.81.8
2.0
4.54.44.54.44.4
6.05.96.05.95.9
4.5I
6.0I
2.0
4.50.00.10.10.1
6.00.00.10.10.1
4.5I
6.0I
6.0
=
V
I
IO=-20 µA
V
IH
or
V
IL
=-4.0 mA 4.184.314.134.10
O
=-5.2 mA 5.685.85.635.60
O
V
=
I
IO=20µA
V
IH
or
V
IL
= 4.0 mA0.170.260.330.40
O
= 5.2 mA0.180.260.330.40
O
VI=VCCor GND±0.1±1±1µA
1.92.01.91.9
0.00.10.10.1
6.0 VI=VCCor GND44080µA
V
V
V
V
4/11
Page 5
M54/M74HC174
AC ELECTRICAL CHARACTERI STI CS (CL=50pF,Inputtr=tf=6ns)
Test ConditionsValue
T
=25oC
SymbolParameter
t
t
TLH
THL
Output Transition
Time
V
CC
(V)
2.0307595110
4.58151922
A
54HC and 74HC
Min.Typ.Max.Min.Max.Min.Max.
6.07131619
t
PLH
t
PHL
Propagation
Delay Time
(CK - Q)
t
PHL
Propagation
Delay Time
(CLR - Q)
f
MAX
Maximum Clock
Frequency
2.068135170205
4.517273441
6.014232935
2.072145180220
4.518293644
6.015253137
2.07.2145.84.8
4.536562924
6.042663428
t
W(H)
t
W(L)
Minimum Pulse
Width
(CLOCK)
t
W(L)
Minimum Pulse
Width
(CLR)
Minimum Set-up
t
s
Time
2.0247595110
4.56151922
6.05131619
2.0247595110
4.56151922
6.05131619
2.0287595110
4.57151922
6.06131619
t
Minimum Hold
h
Time
2.0000
4.5000
6.0000
t
REM
Minimum
Removal Time
2.05555
4.55555
6.05555
C
C
PD
Input Capacitance5101010pF
IN
(*)Power Dissipation
40
Capacitance
(*) CPDisdefined as the value ofthe IC’sinternal equivalent capacitance whichis calculated fromthe operatingcurrentconsumption without load.
(Referto Test Circuit). Average operting current canbe obtained by the followingequation. ICC(opr) = CPD•VCC•fIN+ICC/6(per FLIP/FLOP)
Andthetotal CPDwhen Npcs of FLIP FLOPoperate can be gained bythe followingequation: CPD(total)= 38 +15 xn
Information furnishedis believed to be accurate and reliable. However, SGS-THOMSON Microelectronicsassumes no responsability for the
consequences of useof suchinformation nor forany infringement ofpatents or other rights of third parties which may results from its use. No
license is granted byimplication or otherwiseunder any patentor patent rights ofSGS-THOMSON Microelectronics. Specificationsmentioned
in this publication are subjectto changewithout notice. This publication supersedes andreplaces all information previously supplied.
SGS-THOMSON Microelectronicsproducts are not authorized foruse ascritical componentsinlife supportdevices or systemswithout express
written approval of SGS-THOMSON Microelectonics.
1994SGS-THOMSON Microelectronics- All Rights Reserved
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