Datasheet 74HC 173 Datasheet (FREI)

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT173

Quad D-type flip-flop; positive-edge
trigger; 3-state

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173

FEATURES

• Gated input enable for hold (do nothing) mode

• Gated output enable control

• Edge-triggered D-type register

• Asynchronous master reset

• Output capability: bus driver

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT173 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT173 are 4-bit parallel load registers with
clock enable control, 3-state buffered outputs (Q

to Q3)

0

and master reset (MR).
When the two data enable inputs (E1 andE2) are LOW, the

data on the Dn inputs is loaded into the register

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf=6ns

amb

synchronously with the LOW-to-HIGH clock (CP)
transition. When one or both En inputs are HIGH one
set-up time prior to the LOW-to-HIGH clock transition, the
register will retain the previous data. Data inputs and clock
enable inputs are fully edge-triggered and must be stable
only one set-up time prior to the LOW-to-HIGH clock
transition.

The master reset input (MR) is an active HIGH
asynchronous input. When MR is HIGH, all four flip-flops
are reset (cleared) independently of any other input
condition.

The 3-state output buffers are controlled by a 2-input NOR
gate. When both output enable inputs (OE1 and OE2) are
LOW, the data in the register is presented to the Q

n

outputs. When one or both OEn inputs are HIGH, the
outputs are forced to a high impedance OFF-state. The
3-state output buffers are completely independent of the
register operation; the OEn transition does not affect the
clock and reset operations.

SYMBOL PARAMETER CONDITIONS

t

PHL

f

max

C
C

I
PD

/ t

PLH

propagation delay

CP to Q
MR to Q

n

n

CL= 15 pF; VCC=5V

maximum clock frequency 88 88 MHz
input capacitance 3.5 3.5 pF
power dissipation

notes 1 and 2 20 20 pF

capacitance per flip-flop

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC−1.5 V

ORDERING INFORMATION

TYPICAL

HC HCT

17
13

17
17

UNIT

ns
ns

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

December 1990 2

.

Philips Semiconductors Product specification

Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 2
3, 4, 5, 6 Q
7 CP clock input (LOW-to-HIGH, edge-triggered)
8 GND ground (0 V)
9, 10
14, 13, 12, 11 D
15 MR asynchronous master reset (active HIGH)
16 V

OE1, OE

to Q

0

E1, E

2

to D

0

CC

2

3

output enable input (active LOW)
3-state flip-flop outputs

data enable inputs (active LOW)

3

data inputs

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3

Philips Semiconductors Product specification

Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173

Fig.4 Functional diagram.

FUNCTION TABLE

INPUTS OUTPUTS

REGISTER OPERATING MODES

MR CP E1E2D

n

Qn (register)

reset (clear) H X X X X L
parallel load

hold (no change)

LL↑

LLX

↑

X

lll

l

hXXhX

l
h

X

INPUTS OUTPUTS

3-STATE BUFFER OPERATING MODES

Qn (register) OE1OE2Q0Q1Q2Q

read

disabled

L

H
X

X

L

L

LHLHLHL

L

L

HXXHZZZZZZZ

Notes

1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced input (or output)

one set-up time prior to the LOW-to-HIGH CP transition
X = don’t care
Z = high impedance OFF-state
↑ = LOW-to-HIGH CP transition

L

H

q

n

q

n

3

H

Z

December 1990 4

Philips Semiconductors Product specification

Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173

Fig.5 Logic diagram.

December 1990 5

Philips Semiconductors Product specification

Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: bus driver
ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= 6 ns; CL=50pF

r=tf

SYMBOL PARAMETER

t

PHL

t

PHL

t

PZH

t

PHZ

t

THL

t

W

/ t

/ t

/ t

/ t

propagation delay

PLH

CP to Q

n

propagation delay

MR to Q

3-state output enable time

PZL

OEn to Q

3-state output disable time

PLZ

OEn to Q

output transition time 14

TLH

n

n

n

clock pulse width

HIGH or LOW

t

W

master reset pulse

width; HIGH

t

rem

removal time

MR to CP

t

su

set-up time

En to CP

t

su

set-up time

Dn to CP

(°C)

T

amb

74HC

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

55

80
16
14

80
16
14

60
12
10

100
20
17

60
12
10

20
16

44
16
13

52
19
15

52
19
15

5
4

14
5
4

14
5
4

−8

−3

−2

33
12
10

17
6
5

175
35
30

150
30
26

150
30
26

150
30
26

60
12
10

100
20
17

100
20
17

75
15
13

125
25
21

75
15
13

220
44
37

190
38
33

190
38
33

190
38
33

75
15
13

265
53
45

225
45
38

225
45
38

225
45
38

90
18
15

120
24
20

120
24
20

90
18
15

150
30
26

90
18
15

.

UNIT

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

TEST CONDITIONS

WAVEFORMS

V

CC

(V)

Fig.6

4.5

6.0
Fig.7

4.5

6.0
Fig.8

4.5

6.0
Fig.8

4.5

6.0
Fig.6

4.5

6.0
Fig.6

4.5

6.0
Fig.7

4.5

6.0
Fig.7

4.5

6.0
Fig.9

4.5

6.0
Fig.9

4.5

6.0

December 1990 6

Philips Semiconductors Product specification

Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173

T

SYMBOL PARAMETER

t

h

hold time

En to CP

t

h

hold time

Dn to CP

f

max

maximum clock pulse

frequency

(°C)

amb

74HC

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

0
0
0

1
1
1

6.0
30
35

−17

−6

−5

−11

−4

−3

26
80
95

0
0
0

1
1
1

4.8
24
28

0
0
0

1
1
1

4.0
20
24

UNIT

ns 2.0

ns 2.0

MHz 2.0

TEST CONDITIONS

WAVEFORMS

V

CC

(V)

Fig.9

4.5

6.0
Fig.9

4.5

6.0
Fig.6

4.5

6.0

December 1990 7

Philips Semiconductors Product specification

Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

.

Output capability: bus driver
ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆I

) for a unit load of 1 is given in the family specifications.

CC

To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

OE1,OE
MR
E1, E

2

D

n

CP

2

0.50

0.60

0.40

0.25

1.00

December 1990 8

Philips Semiconductors Product specification

Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= 6 ns; CL=50pF

r=tf

SYMBOL PARAMETER

t

PHL

t

PHL

t

PZH

t

PHZ

t

THL

t

W

/ t

/ t

/ t

/ t

propagation delay

PLH

CP to Q

n

propagation delay

MR to Q

3-state output enable time

PZL

OEn to Q

3-state output disable time

PLZ

OEn to Q

output transition time 5 12 15 19 ns 4.5 Fig.6

TLH

n

n

n

clock pulse width

HIGH or LOW

t

W

master reset pulse

width; HIGH

t

rem

removal time

MR to CP

t

su

set-up time

En to CP

t

su

set-up time

Dn to CP

t

h

hold time

En to CP

t

h

hold time

Dn to CP

f

max

maximum clock pulse

frequency

T

amb

(°C)

TEST CONDITIONS

74HCT

+25 −40 to +85 −40 to +125

UNIT

V

CC

(V)

WAVEFORMS

min. typ. max. min. max. min. max.

20 40 50 60 ns 4.5 Fig.6

20 37 46 56 ns 4.5 Fig.7

20 35 44 53 ns 4.5 Fig.8

19 30 38 45 ns 4.5 Fig.8

16 7 20 24 ns 4.5 Fig.6

15 6 19 22 ns 4.5 Fig.7

12 −2 15 18 ns 4.5 Fig.7

22 13 28 33 ns 4.5 Fig.9

12 7 15 18 ns 4.5 Fig.9

0 −6 0 0 ns 4.5 Fig.9

0 −3 0 0 ns 4.5 Fig.9

30 80 24 20 MHz 4.5 Fig.6

December 1990 9

Philips Semiconductors Product specification

Quad D-type flip-flop; positive-edge trigger;
3-state

AC WAVEFORMS

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

74HC/HCT173

Fig.6 Waveforms showing the clock (CP) to

output (Qn) propagation delays, the clock
pulse width, the output transition times and
the maximum clock pulse frequency.

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.7 Waveforms showing the master reset (MR)

pulse width, the master reset to output (Qn)
propagation delays and the master reset to
clock (CP) removal time.

The shaded areas indicate when the input is permitted to
change for predictable output performance.

(1) HC : V

= 50%; VI= GND to VCC.

M

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.9 Waveforms showing the data set-up and hold

times from input (En, Dn) to clock (CP).

Fig.8 Waveforms showing the 3-state enable and

disable times.

December 1990 10

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

.