Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT126
Quad buffer/line driver; 3-state
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
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December 1990 2
Philips Semiconductors Product specification
Quad buffer/line driver; 3-state 74HC/HCT126
FEATURES
• Output capability: bus driver
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT126 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The HC/HCT126 are four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by
the output enable input (nOE). A LOW at nOE causes the outputs to assume a HIGH impedance OFF-state.
The “126” is identical to the “125” but has active HIGH enable inputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25 °C; tr= tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PDin µW):
PD= CPD× V
CC
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
CL= output load capacitance in pF
VCC= supply voltage in V
∑ (CL× V
CC
2
× fo) = sum of outputs
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay nA to nY CL= 15 pF; VCC= 5 V 9 11 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per buffer notes 1 and 2 23 24 pF
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December 1990 3
Philips Semiconductors Product specification
Quad buffer/line driver; 3-state 74HC/HCT126
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 4, 10, 13 1OE to 4OE output enable inputs (active HIGH)
2, 5, 9, 12 1A to 4A data inputs
3, 6, 8, 11 1Y to 4Y data outputs
7 GND ground (0 V)
14 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
(a)
(b)
Fig.4 Functional diagram.
Fig.5 Logic diagram (one buffer).
FUNCTION TABLE
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
INPUTS OUTPUT
nOE nA nY
H
H
L
L
H
X
L
H
Z
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December 1990 4
Philips Semiconductors Product specification
Quad buffer/line driver; 3-state 74HC/HCT126
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICCcategory: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= tf= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nA to nY
30 100 125 150 ns 2.0 Fig.6
11 20 25 30 4.5
9172126 6.0
t
PZH
/ t
PZL
3-state output
enable time
nOE to nY
41 125 155 190 ns 2.0 Fig.7
15 25 31 38 4.5
12 21 26 32 6.0
t
PHZ
/ t
PLZ
3-state output
disable time
nOE to nY
41 125 155 190 ns 2.0 Fig.7
15 25 31 38 4.5
12 21 26 32 6.0
t
THL
/ t
TLH
output transition
time
14 60 75 90 ns 2.0 Fig.6
5121518 4.5
4101315 6.0
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December 1990 5
Philips Semiconductors Product specification
Quad buffer/line driver; 3-state 74HC/HCT126
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICCcategory: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per unit, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
nA, nOE 1.00
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nA to nY
14 24 30 36 ns 4.5 Fig.6
t
PZH
/ t
PZL
3-state output
enable time
nOE to nY
13 25 31 38 ns 4.5 Fig.7
t
PHZ
/ t
PLZ
3-state output
disable time
nOE to nY
18 28 35 42 ns 4.5 Fig.7
t
THL
/ t
TLH
output transition
time
5 12 15 18 ns 4.5 Fig.6
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December 1990 6
Philips Semiconductors Product specification
Quad buffer/line driver; 3-state 74HC/HCT126
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.6 Waveforms showing the input (nA) to output (nY) propagation delays and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the 3-state enable and disable times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
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