Datasheet 74HC 126 Datasheet (FREI)

Data sheet acquired from Harris Semiconductor

/
j

SCHS144A

November 1997 - Revised May 2000

CD54/74HC126,

CD54/74HCT126

High Speed CMOS Logic
Quad Buffer, Three-State

[ /Title
(CD74
HC126
,
CD74
HCT12

6)
Sub­ect

(High
Speed
CMOS
Logic
Quad
Buffer,
Three­State)

Features

• Three-State Outputs

• Separate Output Enable Inputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

o

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

C to 125oC

OH

Description

The ’HC126 and ’HCT126 contain four independent three­state buffers, each having its own output enable input, which
when “low” puts the output in the high-impedance state.

Ordering Information

TEMP. RANGE

CC

PART NUMBER

CD54HC126F3A -55 to 125 14 Ld CERDIP
CD74HC126E -55 to 125 14 Ld PDIP
CD74HC126M -55 to 125 14 Ld SOIC
CD54HCT126F3A -55 to 125 14 Ld CERDIP
CD74HCT126E -55 to 125 14 Ld PDIP
CD74HCT126M -55 to 125 14 Ld SOIC

NOTES:

1. When ordering,use theentire part number. Addthe suffix96 to
obtain the variant in the tape and reel.

2. Wafer anddie forthis partnumber isavailable whichmeets all
electrical specifications. Please contact yourlocal TIsales office
or customer service for ordering information.

(oC) PACKAGE

Pinout

CD54HC126, CD54HC126

(CERDIP)

CD74HC126, CD74HC126

(PDIP, SOIC)

TOP VIEW

1OE

1
2

1A

3

1Y

4

2OE

5

2A

6

2Y

7

GND

14

V

CC

4OE

13
12

4A
4Y

11

3OE

10

3A

9

3Y

8

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2000, Texas Instruments Incorporated

1

Functional Diagram

1

1OE

2

1A

4

2OE

5

2A

10

3OE

9

3A

13

4OE

12

4A

TRUTH TABLE

INPUTS OUTPUTS

nA nOE nY

CD54/74HC126, CD54/74HCT126

3

1Y

6

2Y

8

3Y

11

4Y

GND = 7

= 14

V

CC

HHH

LHL

XLZ

NOTE:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High Impedance, OFF State

Logic Diagram

nA

nOE

P

nY

n

2

CD54/74HC126, CD54/74HCT126

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD54/74HC126, CD54/74HCT126

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device
Current

Three-State Leakage
Current

I

I

CC

OZ

VCC or

GND

VIL or

V

IH

VCC (V)

0 6 - - 8 - 80 - 160 µA

-6--±0.5 - ±5-±10 µA

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

- - 4.5 to

5.5

V

IL

- - 4.5 to

5.5

V

OH

VIH or

V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

CMOS Loads
High Level Output

-6 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage

V

OL

VIH or

V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

CMOS Loads
Low Level Output

6 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

VCC to

I

0 5.5 - - ±0.1 - ±1-±1 µA

GND

I

CC

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

∆I

CC

V

-2.1

CC

- 4.5 to

5.5
Input Pin: 1 Unit Load
(Note 4)

Three-State Leakage
Current

I

OZ

VIL or

V

IH

- 5.5 - - ±0.5 - ±5-±10 µA

NOTE:

4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

nA, nOE 1

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.

4

CD54/74HC126, CD54/74HCT126

Switching Specifications Input t

, tf = 6ns

r

TEST

PARAMETER SYMBOL

CONDITIONS VCC (V)

HC TYPES

Propagation Delay Data
to Outputs

t

PLH

, t

PHLCL

= 50pF 2 - 100 125 150 ns

4.5 - 20 25 30 ns
CL= 15pF 5 8 - - - ns
CL = 50pF 6 - 17 21 36 ns

Enable Delay Time t

PZL,tPZHCL

= 50pF 2 - 125 155 190 ns

4.5 - 25 31 38 ns
CL= 15pF 5 10 - - - ns
CL = 50pF 6 - 21 26 32 ns

Disabling Delay Time t

PLZ

, t

CL = 50pF 2 - 125 155 190 ns

PHZ

CL= 50pF 4.5 - 25 31 38 ns
CL= 15pF 5 10 - - - ns
CL = 50pF 6 - 21 26 32 ns

Output Transition Times t

TLH

, t

THLCL

= 50pF 2 - 60 75 90 ns

4.5 - 12 15 18 ns

6 - 10 13 15 ns
Input Capacitance C
Three-State Output

I

C

O

---1010 10pF

---2020 20pF

Capacitance
Power Dissipation

C

PD

- 5 30 - - - pF
Capacitance
(Notes 5, 6)

HCT TYPES

Propagation Delay Time
to Outputs

Output Enable Time t

t

, t

PLH

PHLCL

PZL,tPZHCL

= 50pF 4.5 - 24 30 36 ns

CL= 15pF 5 9 - - - ns

= 50pF 4.5 - 25 31 38 ns

CL= 15pF 5 10 - - - ns

Output Disabling Time t

PLZ

, t

PHZCL

= 50pF 4.5 - 28 35 42 ns

CL= 15pF 5 11 - - - ns
Output Transition Times t
Input Capacitance C
Three-State Output

TLH

, t

THLCL

I

C

O

= 50pF 4.5 - 12 15 18 ns

---1010 10pF

---2020 20pF

Capacitance
Power Dissipation

C

PD

- 5 36 - - - pF
Capacitance
(Notes 5, 6)

NOTES:

5. CPD is used to determine the dynamic power consumption, per multiplexer.

6. PD = V

2

fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

25oC -40oC TO 85oC -55oC TO 125oC

UNITSTYP MAX MAX MAX

5

CD54/74HC126, CD54/74HCT126

Test Circuits and Waveforms

tr = 6ns tf = 6ns

INPUT

90%
50%
10%

V

CC

GND

tr = 6ns

INPUT

2.7V

1.3V

0.3V

= 6ns

t

f

3V

GND

INVERTING

OUTPUT

t

THL

t

PHL

t

PLH

50%

10%

90%

t

TLH

FIGURE 1. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6ns 6ns

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

50%

t

t

OUTPUTS
ENABLED

PLZ

PHZ

10%

90%

90%

10%

t

PZL

t

PZH

OUTPUTS

DISABLED

50%

50%

FIGURE 3. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

V

CC

GND

OUTPUTS
ENABLED

t

INVERTING

OUTPUT

THL

t

PHL

t

PLH

1.3V

10%

90%

t

TLH

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

0.3

t

t

PZH

6ns

PZL

1.3V

1.3V
OUTPUTS

ENABLED

t

r

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

t

t

OUTPUTS
ENABLED

6ns t

PLZ

PHZ

10%

90%

f

2.7

1.3

OUTPUTS

DISABLED

FIGURE 4. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

3V

GND

NOTE: Open drain waveforms t
VCC, CL = 50pF.

FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

TIED HIGH

OR LOW

and t

PLZ

OTHER

INPUTS

OUTPUT

DISABLE

PZL

IC WITH

THREE-

STATE

OUTPUT

are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto

OUTPUT
R

= 1kΩ

L

C

L

50pF

VCC FOR t
GND FOR t

PLZ

PHZ

AND t

AND t

PZL

PZH

6

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  2000, Texas Instruments Incorporated