Datasheet 74FST3345 Datasheet (ON Semiconductor)

74FST3345

8−Bit Bus Switch

The ON Semiconductor 74FST3345 is an 8−bit, high performance
switch. The device is CMOS TTL compatible when operating between
4 and 5.5 Volts. The device exhibits extremely low RON and adds
nearly zero propagation delay. The device adds no noise or ground
bounce to the system.

The device consists of an 8−bit switch with two Output/Enable pins
(OE and OE

Features

• R

ON

• Less Than 0.25 ns−Max Delay Through Switch

• Nearly Zero Standby Current

• No Circuit Bounce

• Control Inputs are TTL/CMOS Compatible

• Pin−For−Pin Compatible with QS3345, FST3345, CBT3345

• All Popular Packages: QSOP−20, TSSOP−20, SOIC−20

• All Devices in Package TSSOP are Inherently Pb−Free*

).

 4  Typical

OE

A
A
A
A
A
A
A
A

GND

1
2

0

3

1

4

2

5

3

6

4

7

5

8

6

9

7

10

20
19
18
17
16
15
14
13
12
11

V
OE
B
B
B
B
B
B
B
B

CC

0
1
2
3
4
5
6
7

Figure 1. 20−Lead Pinout

20

20

20

QS SUFFIX

CASE 492A

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1

SOIC−20
DW SUFFIX
CASE 751D

1

TSSOP−20
DT SUFFIX

CASE 948E

1

QSOP−20

MARKING

DIAGRAMS

20

FST3345

AWLYYWW

1

20

FST

3345

ALYW

1

20

FST3345

AWLYWW

1

218

A

0

9

A

7

1

OE

19

OE

B

0

11

B

7

Figure 2. Logic Diagram

TRUTH TABLE

Inputs

OE

X
H

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2005

January, 2005 − Rev. 1

OE

L
X

L

H

Function

Connect
Connect

Disconnect

1 Publication Order Number:

A = Assembly Location
L, WL = Wafer Lot
Y = Year
W, WW = Work Week

PIN NAMES

Pin

OE1, OE
1A, 2A
1B, 2B Bus B

2

Description

Bus Switch Enables

Bus A

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.

74FST3345/D

74FST3345

MAXIMUM RATINGS

Symbol Parameter Value Unit

V

V

V

I

I

OK

I

I

CC

I

GND

T

STG

T
T



MSL Moisture Sensitivity Level 1

F

V

ESD

I

Latchup

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously . If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.

1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.

2. Tested to EIA/JESD22−A114−A.

3. Tested to EIA/JESD22−A115−A.

4. Tested to EIA/JESD78.

DC Supply Voltage 0.5 to 7.0 V

CC

DC Input Voltage 0.5 to 7.0 V

I

DC Output Voltage 0.5 to 7.0 V

O

DC Input Diode Current VI  GND 50 mA

IK

DC Output Diode Current VO  GND 50 mA
DC Output Sink Current 128 mA

O

DC Supply Current per Supply Pin 100 mA
DC Ground Current per Ground Pin 100 mA
Storage Temperature Range 65 to 150 C
Lead Temperature, 1 mm from Case for 10 Seconds 260 C

L

Junction Temperature Under Bias 150 C

J

Thermal Resistance (Note 1) SOIC

JA

TSSOP

QSOP

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

R

ESD Withstand Voltage Human Body Model (Note 2)

Machine Model (Note 3)

96
128
200

2000

200

Latchup Performance Above VCC and Below GND at 85C (Note 4) 500 mA

C/W

V

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

V

V

T

t/V Input Transition Rise or Fall Rate Switch Control Input

5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.

Supply Voltage Operating, Data Retention Only 4.0 5.5 V

CC

Input Voltage (Note ) 0 5.5 V

I

Output Voltage (HIGH or LOW State) 0 V

O

Operating Free−Air Temperature 40 85 C

A

0

Switch I/O

0

CC

5

DC

V

ns/V

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2

74FST3345

†

DC ELECTRICAL CHARACTERISTICS

V

CC

Symbol Parameter Conditions (V) Min Typ* Max Unit

V

Clamp Diode Resistance IIN = 18mA 4.5 1.2 V

IK

V

High−Level Input Voltage 4.0 to 5.5 2.0 V

IH

V

Low−Level Input Voltage 4.0 to 5.5 0.8 V

IL

I

Input Leakage Current 0  VIN  5.5 V 5.5 1.0 A

I

I

OFF−STATE Leakage Current 0  A, B  V

OZ

R

Switch On Resistance (Note 6) VIN = 0 V, IIN = 64 mA 4.5 4 7 

ON

CC

5.5 1.0 A

VIN = 0 V, IIN = 30 mA 4.5 4 7
VIN = 2.4 V, IIN = 15 mA 4.5 8 15
VIN = 2.4 V, IIN = 15 mA 4.0 11 20

I

Quiescent Supply Current VIN = VCC or GND, I

CC

I

Increase In ICC per Input One input at 3.4 V, Other inputs at VCC or GND 5.5 2.5 mA

CC

= 0 5.5 3 A

OUT

*Typical values are at VCC = 5.0 V and TA = 25C.

6. Measured by the voltage drop between A and B pins at the indicated current through the switch.

AC ELECTRICAL CHARACTERISTICS

VCC = 4.5 to 5.5 V VCC = 4.0 V

Symbol Parameter Conditions Figures Min Max Min Max Unit

t

,

PHL

t

t

PZH

t

t

PHZ

t

Prop Delay Bus to Bus
(Note 7)

PLH

,

Output Enable Time VI = 7 V for t

PZL

,

Output Disable Time VI = 7 V for t

PLZ

7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).

VI = OPEN 3 and 4 0.25 0.25 ns

VI = OPEN for t

VI = OPEN for t

PZL

PLZ

PZH

PHZ

3 and 4 1.5 6.5 7.0 ns

3 and 4 1.0 8.0 8.2 ns

TA = 40C to 85C

Limits

TA = 40C to 85C

CAPACITANCE (Note 8)

Symbol Parameter Conditions Typ Max Unit

C

C

Control Pin Input Capacitance VCC = 5.0 V 3 pF

IN

Input/Output Capacitance VCC, OE = 5.0 V 5 pF

I/O

8. TA = 25C, f = 1 MHz, Capacitance is characterized but not tested.

ORDERING INFORMATION

Device Order Number Package Shipping

74FST3345DW SOIC−20 38 Units / Rail
74FST3345DWR2 SOIC−20 1000 Units / Tape & Reel
74FST3345DT TSSOP−20*

75 Units / Rail

(Pb−Free)

74FST3345DTR2 TSSOP−20*

2500 Units / Tape & Reel

(Pb−Free)
74FST3345QS QSOP−20 55 Units / Rail
74FST3345QSR QSOP−20 2500 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

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74FST3345

AC Loading and Waveforms

V

I

FROM

OUTPUT

UNDER

TEST

CL*

NOTES:

1. Input driven by 50  source terminated in 50 .

2. CL includes load and stray capacitance.
*C

= 50 pF

L

Figure 3. AC Test Circuit

t

= 2.5 nS

f

90 %

SWITCH
INPUT

OUTPUT

90 %

10 % 10 %
t

PLH

1.5 V 1.5 V

500 

500 

t

= 2.5 nS

f

3.0 V

1.5 V1.5 V
GND

t

PLH

V

OH

V

OL

ENABLE
INPUT

t

= 2.5 nS

f

OUTPUT

OUTPUT

Figure 4. Propagation Delays

90 %

1.5 V
10 %10 %

t

PZL

1.5 V

t

PZH

1.5 V

90 %

1.5 V

t

= 2.5 nS

f

t

PZL

t

PHZL

3.0 V

GND

V

OL

V

OL

V

OH

V

OH

+ 0.3 V

− 0.3 V

Figure 5. Enable/Disable Delays

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74FST3345

PACKAGE DIMENSIONS

SOIC−20

DW SUFFIX

CASE 751D−05

ISSUE G

H10X

M

B

M

0.25

D

20

A

11





E

1

B20X

M

T

0.25

SAS

B

10

B

h X 45

A

L

18X

SEATING

e

A1

T

PLANE

C

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.

MILLIMETERS

DIM MIN MAX

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90

 0 7



TSSOP−20
DT SUFFIX

CASE 948E−02

ISSUE B

20X REFK

S

U0.15 (0.006) T

0.10 (0.004) V

M

S

U

T

S

K

2X

L/2

L

PIN 1
IDENT

110

1120

B

JJ1

−U−

N

S

U0.15 (0.006) T

A

K1

SECTION N−N

0.25 (0.010)

M

−V−
N

F

DETAIL E

C

G

H

DETAIL E

0.100 (0.004)

−T−

SEATING
PLANE

D

NOTES:

1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION:
MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.

4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.

5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.

6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.

MILLIMETERS

−W−

DIMAMIN MAX MIN MAX

B 4.30 4.50 0.169 0.177
C 1.20 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

6.60 0.260

6.40 0.252

−−− −−−



INCHES

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5

74FST3345

PACKAGE DIMENSIONS

QSOP−20

QS SUFFIX

CASE 492A−01

ISSUE O

−B−

L

P

0.25 (0.010) T

C

0.25 (0.010) T BA

−A−
R

G

M

U

Q

H x 45

RAD.

0.013 X 0.005
DP. MAX

RAD.

0.005−0.010
TYP

DETAIL E



MOLD PIN
MARK

V

N

8 PL

K

J

M

−T−

D20 PL

M

S S

SEATING
PLANE

F

DETAIL E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN
THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE
ONLY). BOTTOM PACKAGE DIMENSION SHALL
FOLLOW THE DIMENSION STATED IN THIS
DRAWING.

4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD
FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 6 MILS PER
SIDE.

5. BOTTOM EJECTOR PIN WILL INCLUDE THE
COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D.

8



8



MILLIMETERS

MIN




0 8 0



INCHES

DIM MAXMINMAX

A 8.56 8.740.337 0.344
B 3.81 3.990.150 0.157
C 1.55 1.730.061 0.068
D 0.20 0.310.008 0.012
F 0.41 0.890.016 0.035
G 0.64 BSC0.025 BSC
H 0.20 0.460.008 0.018
J 0.249 0.1910.0098 0.0075
K 0.10 0.250.004 0.010

L 5.84 6.200.230 0.244
M 0 8 0
N 0 7 0 7
P 1.32 1.580.052 0.062
Q 0.89 DIA0.035 DIA
R 0.89 1.140.035 0.045
U 0.89 1.140.035 0.045
V

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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