Datasheet 74FST3245QSR, 74FST3245QS, 74FST3245DWR2, 74FST3245DW, 74FST3245DTR2 Datasheet (ON Semiconductor)

74FST3245

8-Bit Bus Switch

The ON Semiconductor 74FST3245 is an 8–bit, high performance
switch. The device is CMOS TTL compatible when operating between
4 and 5.5 Volts. The device exhibits extremely low RON and adds
nearly zero propagation delay. The device adds no noise or ground
bounce to the system.

The device consists of an 8–bit switch. Port A is connected to Port B
when OE

• R

• Less Than 0.25 ns–Max Delay Through Switch

• Nearly Zero Standby Current

• No Circuit Bounce

• Control Inputs are TTL/CMOS Compatible

• Pin–For–Pin Compatible with QS3245, FST3245, CBT3245

• All Popular Packages: QSOP–20, TSSOP–20, SOIC–20

is low. If OE is high, the switch is high Z.

 4  Typical

ON

20

SO–20
DW SUFFIX
CASE 751D

http://onsemi.com

20

1

1

MARKING

DIAGRAMS

FST3245

AWLYYWW

1

NC

2

A

0

3

A

1

4

A

2

5

A

3

6

A

4

7

A

5

8

A

6

9

A

7

GND

10

Figure 1. 20–Lead Pinout

19

OE

2

A

0

9

A

7

Figure 2. Logic Diagram

20
19
18
17
16
15
14
13
12
11

V
OE
B
B
B
B
B
B

B
B

CC

0
1
2
3
4
5
6
7

18

11

20

1

TSSOP–20
DT SUFFIX

CASE 948E

20

1

QSOP–20
QS SUFFIX
CASE 492A

A = Assembly Location
L, WL = Wafer Lot
Y = Year

B

0

W, WW = Work Week

20

FST

3245

ALYW

1

20

FST3245

AWLYWW

1

PIN NAMES

Pin

OE1, OE

B

7

1A, 2A
1B, 2B Bus B

2

Description

Bus Switch Enables

Bus A

TRUTH TABLE

Input OE Function

L

H

 Semiconductor Components Industries, LLC, 2001

August, 2001 – Rev. 0

Connect

Disconnect

ORDERING INFORMATION

Device Package Shipping

74FST3245DW SO–20 38 Units/Rail
74FST3245DWR2 SO–20
74FST3245DT TSSOP–20

74FST3245DTR2 TSSOP–20 2500 Units/Reel
74FST3245QS QSOP–20 55 Units/Rail
74FST3245QSR QSOP–20 2500 Units/Reel

1 Publication Order Number:

1000 Units/Reel

75 Units/Rail

74FST3245/D

74FST3245

MAXIMUM RATINGS

Symbol Parameter Value Unit

V

CC

V

I

V

O

I

IK

I

OK

I

O

I

CC

I

GND

T

STG

T

L

T

J



JA

MSL Moisture Sensitivity Level 1
F

R

V

ESD

I

LATCH–UP

Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.

1. Measured with minimum pad spacing on an FR4 board, using 10 mm–by–1 inch, 2–ounce copper trace with no air flow.

2. Tested to EIA/JESD22–A114–A.

3. Tested to EIA/JESD22–A115–A.

4. Tested to EIA/JESD78.

DC Supply Voltage –0.5 to 7.0 V
DC Input Voltage –0.5 to 7.0 V
DC Output Voltage –0.5 to 7.0 V
DC Input Diode Current VI  GND –50 mA
DC Output Diode Current VO  GND –50 mA
DC Output Sink Current 128 mA
DC Supply Current per Supply Pin 100 mA
DC Ground Current per Ground Pin 100 mA
Storage Temperature Range –65 to 150 C
Lead Temperature, 1 mm from Case for 10 Seconds 260 C
Junction Temperature Under Bias 150 C
Thermal Resistance (Note 1) SOIC

TSSOP

QSOP

96
128
200

C/W

Flammability Rating Oxygen Index: 28 to 34 UL 94 V–0 @ 0.125 in
ESD Withstand Voltage Human Body Model (Note 2)

Machine Model (Note 3)

2000

200

V

Latch–Up Performance Above VCC and Below GND at 85C (Note 4) 500 mA

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

CC

V

I

V

O

T

A

t/V Input Transition Rise or Fall Rate Switch Control Input

5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.

Supply Voltage Operating, Data Retention Only 4.0 5.5 V
Input Voltage (Note ) 0 5.5 V
Output Voltage (HIGH or LOW State) 0 V

CC

Operating Free–Air Temperature –40 85 C

Switch I/O

0
0

5

DC

V

ns/V

http://onsemi.com

2

74FST3245

DC ELECTRICAL CHARACTERISTICS

V

CC

Symbol Parameter Conditions (V) Min Typ* Max Unit

V

IK

V

IH

V

IL

I

I

I

OZ

R

ON

Clamp Diode Resistance IIN = –18mA 4.5 –1.2 V
High–Level Input Voltage 4.0 to 5.5 2.0 V
Low–Level Input Voltage 4.0 to 5.5 0.8 V
Input Leakage Current 0  VIN  5.5 V 5.5 1.0 A
OFF–STATE Leakage Current 0  A, B  V

CC

5.5 1.0 A

Switch On Resistance (Note 6) VIN = 0 V, IIN = 64 mA 4.5 4 7 

VIN = 0 V, IIN = 30 mA 4.5 4 7
VIN = 2.4 V, IIN = 15 mA 4.5 8 15
VIN = 2.4 V, IIN = 15 mA 4.0 11 20

I

CC

I

Quiescent Supply Current VIN = VCC or GND, I
Increase In ICC per Input One input at 3.4 V, Other inputs at VCC or GND 5.5 2.5 mA

CC

= 0 5.5 3 A

OUT

*Typical values are at VCC = 5.0 V and TA = 25C.

6. Measured by the voltage drop between A and B pins at the indicated current through the switch.

AC ELECTRICAL CHARACTERISTICS

VCC = 4.5 to 5.5 V VCC = 4.0 V

Symbol Parameter Conditions Figures Min Max Min Max Unit

t

,

t
t

t
t

t

PHL
PLH

PZH
PZL

PHZ
PLZ

Prop Delay Bus to Bus
(Note 7)

,

Output Enable Time VI = 7 V for t

,

Output Disable Time VI = 7 V for t

7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).

VI = OPEN 3 and 4 0.25 0.25 ns

VI = OPEN for t

VI = OPEN for t

PZL

PLZ

PZH

PHZ

3 and 4 1.5 5.9 6.4 ns

3 and 4 1.5 6.0 5.7 ns

TA = –40C to 85C

Limits

TA = –40C to 85C

CAPACITANCE (Note 8)

Symbol Parameter Conditions Typ Max Unit

C

IN

C

I/O

Control Pin Input Capacitance VCC = 5.0 V 3 pF
Input/Output Capacitance VCC, OE = 5.0 V 5 pF

8. TA = 25C, f = 1 MHz, Capacitance is characterized but not tested.

http://onsemi.com

3

74FST3245

AC Loading and Waveforms

V

I

FROM

OUTPUT

UNDER

TEST

CL*

NOTES:

1. Input driven by 50  source terminated in 50 .

2. CL includes load and stray capacitance.
*C

= 50 pF

L

Figure 3. AC Test Circuit

t

= 2.5 nS

f

90 %

SWITCH
INPUT

OUTPUT

90 %

10 % 10 %
t

PLH

1.5 V 1.5 V

500 

500 

t

= 2.5 nS

f

3.0 V

1.5 V1.5 V
GND

t

PLH

V

OH

V

OL

ENABLE
INPUT

t

= 2.5 nS

f

OUTPUT

OUTPUT

Figure 4. Propagation Delays

90 %

1.5 V
10 %10 %

t

PZL

1.5 V

t

PZH

1.5 V

90 %

1.5 V

t

= 2.5 nS

f

t

PZL

t

PHZL

3.0 V

GND

V

OL

V

OL

V

OH

V

OH

+ 0.3 V

– 0.3 V

Figure 5. Enable/Disable Delays

http://onsemi.com

4

74FST3245

PACKAGE DIMENSIONS

SO–20

DW SUFFIX

CASE 751D–05

ISSUE F

H10X

M

B

M

0.25

D

20

1

B20X

M

SAS

T

0.25

18X

e

A

11



E

10

h X 45

B

B

A

SEATING
PLANE

A1

T



NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.

MILLIMETERS

DIM MIN MAX

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55

L

C

h 0.25 0.75
L 0.50 0.90

 0 7



http://onsemi.com

5

74FST3245

PACKAGE DIMENSIONS

TSSOP–20
DT SUFFIX

CASE 948E–02

ISSUE A

20X REFK

S

U0.15 (0.006) T

0.10 (0.004) V

M

S

U

T

S

K

2X

L/2

L

PIN 1
IDENT

110

1120

B

JJ1

–U–

N

S

U0.15 (0.006) T

A

K1

SECTION N–N

0.25 (0.010)

M

–V–

N

F

DETAIL E

C

G

H

DETAIL E

0.100 (0.004)

SEATING

–T–

PLANE

D

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.

MILLIMETERS

–W–

DIMAMIN MAX MIN MAX

B 4.30 4.50 0.169 0.177
C 1.20 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

6.60 0.260

6.40 0.252

--- ---



INCHES

http://onsemi.com

6

–B–

L

P

0.25 (0.010) T

C

0.25 (0.010) T BA

74FST3245

PACKAGE DIMENSIONS

QSOP–20

QS SUFFIX

CASE 492A–01

–A–

R

G

M

D20 PL

M

S S

U

K

Q

0.013 X 0.005

0.005–0.010

–T–

SEATING
PLANE

H x 45

RAD.

DP. MAX

RAD.

TYP

DETAIL E



MOLD PIN
MARK

V

N

8 PL

J

M

F

DETAIL E

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN
THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE
ONLY). BOTTOM PACKAGE DIMENSION SHALL
FOLLOW THE DIMENSION STATED IN THIS
DRAWING.

4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD
FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 6 MILS PER
SIDE.

5. BOTTOM EJECTOR PIN WILL INCLUDE THE
COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D.

8



8



MILLIMETERS

MIN




0 8 0



INCHES

DIM MAXMINMAX

A 8.56 8.740.337 0.344
B 3.81 3.990.150 0.157
C 1.55 1.730.061 0.068
D 0.20 0.310.008 0.012

F 0.41 0.890.016 0.035
G 0.64 BSC0.025 BSC
H 0.20 0.460.008 0.018

J 0.249 0.1910.0098 0.0075
K 0.10 0.250.004 0.010

L 5.84 6.200.230 0.244
M 0 8 0
N 0 7 0 7

P 1.32 1.580.052 0.062
Q 0.89 DIA0.035 DIA
R 0.89 1.140.035 0.045
U 0.89 1.140.035 0.045

V

http://onsemi.com

7

74FST3245

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

Literature Fulfillment:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA

Phone: [phone] or 800–344–3860 Toll Free USA/Canada
Fax: [phone] or 800–344–3867 Toll Free USA/Canada
Email: [e-mail]

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

http://onsemi.com

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031

Phone: [phone]
Email: [e-mail]

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

74FST3245/D

8