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© 1999 Fairchild Semiconductor Corporation DS010913 www.fairchildsemi.com
April 1991
Revised August 1999
74FR9244 9-Bit Buffer/Line Driver with 3-STATE Outputs
74FR9244
9-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The 74FR9244 is a non-inverting 9-bit buffer and line driver
designed to be employed as memor y and address driver,
clock driver and bus-oriented transmitter/receiver.
Features
■ 3-STATE outputs drive bus lines or buffer memory
address registers
■ Outputs sink 64 mA and source 15 mA
■ Guaranteed multiple output switching, 250 pf delays and
pin-to-pin skew
■ Guarante ed 4000V minimum ESD protection
■ 9-Bit architecture for systems carrying parity
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram Pin Descriptions
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Order Number Package Number Package Description
74FR9244SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74FR9244SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Pin Names Description
OE
1
,–OE2Output Enable Input (Active-LOW)
I
0–I8
Inputs
O
0–O8
Outputs
OE
1
OE
2
I
n
O
n
HXXZ
XHXZ
LLHH
LLLL
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74FR9244
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditi ons is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in put s .
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature Under Bias −55°C to +125°C
Junction Temperature Under Bias −55°C to +150°C
V
CC
Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
CC
3-STATE Outp ut −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) Twice The Rated I
OL
(mA)
ESD Last Passing Voltage (Min) 4000V
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
V
OH
Output HIGH Voltage 2.4 V Min IOH = −3 mA
2.0 V Min IOH = −15 mA
V
OL
Output LOW Voltage 0.55 V Min IOL = 64 mA
I
IH
Input HIGH Current 5 µAMaxVIN = 2.7V
I
BVI
Input HIGH Current Breakdown Test 7 µAMaxVIN = 7.0V
I
IL
Input LOW Current −150 µAMaxVIN = 0.5V
V
ID
Input Leakage Test 4.75 V 0.0 IID = 1.9 µA,
All Other Pins Grounded
I
OD
Output Circuit Leakage Current 3.75 µA0.0V
IOD
= 150 mV,
All Other Pins Grounded
I
OZH
Output Leakage Current 20 µAMaxV
OUT
= 2.7V
I
OZL
Output Leakage Current −20 µAMaxV
OUT
= 0.5V
I
OS
Output Short-Circuit Current −100 −225 mA Max V
OUT
= 0.0V
I
CEX
Output HIGH Leakage Current 50 µAMaxV
OUT
= V
CC
I
ZZ
Bus Drainage Test 100 µA0.0V
OUT
= 5.25V
I
CCH
Power Supply Current 30 40 mA Max All Outputs HIGH
I
CCL
Power Supply Current 60 75 mA Max All Outputs LOW
I
CCZ
Power Supply Current 35 45 mA Max Outputs 3-STATED
C
IN
Input Capacitance 8.0 pF 5.0
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74FR9244
AC Electrical Characteristics
Extended AC Characteristics
Note 3: This specific ation i s guar anteed but n ot tes ted. Th e limits apply to p ropagat ion del ays fo r all paths d escrib ed swit ching in phas e, i.e., all LOW-to-
HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc.
Note 4: These specific ations guaran teed but no t tested. The limits repres ent propaga tion delays with 250 pF load capacito rs in place of th e 50 pF load
capacitors in the standard AC load. This spe c if ic at ion pertains to single output switching only.
Note 5: Skew is def ined as the abs olute value of the difference betwee n the actual pro pagation delays fo r any two outputs of the same dev ic e. T he specifi-
cation applies to any outputs switching HIGH-to-LOW, (t
OSHL
), LOW-to-HIGH, (t
OSLH
), or HIGH-to-LOW and/or LOW-to-HIGH, (t
OST
). Specification guar an-
teed with all outputs sw it c hing in phase.
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
t
PLH
Propagation Delay 1.0 2.6 4.1 1.0 4.1
ns
t
PHL
1.01.84.11.04.1
t
PZH
Output Enable Time 2.6 4.8 7.0 2.6 7.0
ns
t
PZL
2.63.97.02.67.0
t
PHZ
Output Disable Time 1.6 3.7 6.1 1.6 6.1
ns
t
PLZ
1.63.66.11.66.1
Symbol Parameter
TA = 0°C to +70°CT
A
= 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 250 pF
Eight Outputs Switching (Note 4)
(Note 3)
Min Max Min Max
t
PLH
Propagation Delay 1.0 6.0 2.3 8.0
ns
t
PHL
1.06.02.38.0
t
PZH
Output Enable Time 2.6 8.5
ns
t
PZL
2.6 8.5
t
PHZ
Output Disable Time 1.6 6.5
ns
t
PLZ
1.6 6.5
t
OSHL
Pin-to-Pin Skew
1.3 ns
for HL Transitions (Note 5)
t
OSLH
Pin-to-Pin Skew
1.7 ns
for LH Transitions (Note 5)
t
OST
Pin-to-Pin Skew
3.0 ns
for HL/LH Transitions (Note 5)
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74FR9244
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
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74FR9244 9-Bit Buffer/Line Driver with 3-STAT E Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent license s are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided i n the labe li ng, can be re asonably expected to result in a significant injury to the
user.
2. A critical componen t in any com ponent o f a l ife supp ort
device or system whose failu re to perform can b e reasonably expected to c ause th e fa i lure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
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