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© 1999 Fairchild Semiconductor Corporation DS009595 www.fairchildsemi.com
April 1988
Revised August 1999
74F821 10-Bit D-Type Flip-Flop
74F821
10-Bit D-Type Flip-Flop
General Description
The 74F821 is a 10-bit D-type flip-flop with 3-STATE true
outputs arranged in a broadside pinout.
Features
■ 3-STATE Outputs
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F821SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F821SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
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74F821
Unit Loading/Fan Out
Functional Description
The 74F821 consists of ten D-type edge-triggered flipflops. This device has 3-STATE true outputs for bus systems organized i n a b ro ads id e pinn i ng. Th e buff ere d Cl ock
(CP) and buffered Output Enable (OE
) are common to all
flip-flops. The flip-flops will store the state of their individual
D inputs that meet the setup and hold times requirements
on the LOW-to-HIGH CP transition. With th e OE
LOW the
content of the flip-flop s are available at the outp uts. When
the OE
is HIGH, the outputs go to the high impedance
state. Op eration of the OE
input does not affect the state of
the flip-flops.
Function Table
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.
Pin Names Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
D0–D
9
Data Inputs 1.0/1.0 20 µA/−0.6 mA
OE
Output Enable
1.0/1.0 20 µA/−0.6 mA
3-STATE Input
CP Clock Input 1.0/1.0 20 µA/−0.6 mA
O
0–O9
3-STATE Outputs 150/40 (33.3) −3.0 mA/24 mA (20 mA)
Inputs Internal Output
Function
OE
CP D Q O
H H X NC Z Hold
H L X NC Z Hold
H
L H Z Load
H
H L Z Load
L
L H L Data Available
L
H L H Data Available
L H X NC NC No Change in Data
L L X NC NC No Change in Data
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74F821
Absolute Maximum Ratings(Note 1) Recomm ended Operating
Conditions
Note 1: Absolute maximum ratings are values beyon d which the device
may be damaged or have its useful life impaired . Functional operation
under these condit ions is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V
CC
Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
CC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
Free Air Ambi ent Temperat ure 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
V
OH
Output HIGH 10% V
CC
2.5
VMin
IOH = −1 mA
Voltage 10% V
CC
2.4 IOH = −3 mA
5% V
CC
2.7 IOH = −1 mA
5% V
CC
2.7 IOH = −3 mA
V
OL
Output LOW
10% V
CC
0.5 V Min IOL = 24 mA
Voltage
I
IH
Input HIGH Current
5.0 µAMaxVIN = 2.7V
I
BVI
Input HIGH Current
7.0 µAMaxVIN = 7.0V
Breakdown Test
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
IID = 1.9 µA,
Test All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current −0.6 mA Max VIN = 0.5V
I
OZH
Output Leakage Current 50 µAMaxV
OUT
= 2.7V
I
OZL
Output Leakage Current −50 µAMaxV
OUT
= 0.5V
I
OS
Output Short-Circuit Current −60 −150 mA Max V
OUT
= 0V
I
CCZ
Power Supply Current 78 100 mA Max VO = HIGH Z
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74F821
AC Electrical Characteristics
AC Operating Requirements
Symbol Parameter
TA = +25°CT
A
= −55°C to +125°CTA = 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF CL = 50 pF
Min Typ Max Min Max Min Max
f
MAX
Maximum Clock Frequency 100 150 60 70 MHz
t
PLH
Propagation Delay 2.0 6.4 9.5 2.0 10.5 2.0 10.5
ns
t
PHL
CP to O
n
2.0 6.2 9.5 2.0 10.5 2.0 10.5
t
PZH
Output Enable Time 2.0 5.8 10.5 2.0 13.0 2.0 11.5
t
PZL
OE to O
n
2.0 6.3 10.5 2.0 13.0 2.0 11.5
ns
t
PHZ
Output Disable Time 1.5 3.4 7.0 1.0 7.5 1.5 7.5
t
PLZ
OE to O
n
1.53.57.01.07.51.57.5
Symbol Parameter
TA = +25°CTA = −55°C to +125°CTA = 0°C to +70°C
UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V
Min Max Min Max Min Max
tS(H) Setup Time, HIGH or LOW 2.5 4.0 3.0
tS(L) Dn to CP 2.5 4.0 3.0
ns
tH(H) Hold Time, HIGH or LOW 2.5 2.5 2.5
tH(L) Dn to CP 2.5 2.5 2.5
tW(H) CP Pulse Width 5.0 6.0 6.0
ns
tW(L) HIGH or LOW 5.0 6.0 6.0
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74F821
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
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74F821 10-Bit D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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