Datasheet 74F794SCX, 74F794SC, 74F794PC Datasheet (Fairchild Semiconductor)

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© 1999 Fairchild Semiconductor Corporation DS010652 www.fairchildsemi.com
March 1990 Revised August 1999
74F794 8-Bit Register with Readback
74F794 8-Bit Register with Readback
General Description
The 74F794 is an 8-bit register with readback capability designed to store data as well as read the register informa­tion back onto the data bus. The I/O bus (D bus) has 3­STATE outputs. Current sinking capability is 64 mA on both the D and Q busses.
Data is loaded into the registers on the LOW-to-HIGH tran­sition of the clock (CP). The outp ut enable (OE
) is used to
enable data on D
0–D7
. When OE is LOW, the output of the
registers is enabled on D
0–D7
, enabling D as an outp ut
bus. When OE is HIGH, D
0–D7
are inputs to t he registers
configuring D as an input bus.
Features
3-STATE outputs on the I/O port
D and Q output sink capability of 64 mA
Functionally and pin equivalent to the 74LS794
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbol Connection Diagram
Order Number Package Number Package Description
74F794SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F794PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74F794
Input Loading/Fan-Out
Truth Table
Note 1: In this case the output of the regi ster is clocked t o the inputs an d
the overall Q output is unc hanged at Q
n
.
Logic Diagram
Pin Names Description
HIGH/LOW
(U.L.) Current
OE
Output Enable Input 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Inputs 1.0/1.0 20 µA/−0.6 mA D
0–D7
D Bus Inputs/ 3.5/1.083 70 µA/650 µA
3-STATE Outputs 750/106.6 15 mA/64 mA Q
0–Q7
Q Bus Outputs 750/106.6 15 mA/64 mA
Inputs Outputs
CP OE
QD
L or H or LQ
n
Output, Q
L or H or HQ
n
Input
LQ
n
Output, Q (Note 1)
H D Input
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74F794
Absolute Maximum Ratings(Note 2) Recommended Operating
Conditions
Note 2: Absolute maximum ratings are values beyon d which the device
may be damaged or have its useful life impaired . Functional operation under these condit ions is not implied.
Note 3: In this case the output of the regist er is clocked to the inputs and the overall Q output is unchanged at Q
n
.
Note 4: Either voltage limit or curren t limit is sufficient to protect in puts.
DC Electrical Characteristics over Operating Temperature Range unless otherwise specified
Storage Temperature 65°C to + 150°C Ambient Temperature under Bias 55° to +125°C Junction Temperature under Bias 55°C to +150°C V
CC
Pin Potential to Ground Pin 0.5V to +7.0V Input Voltage (Note 3) 0.5V to +7.0V Input Current (Note 3) 30 mA to +5.0 mA ESD Last Passing Voltage (Min) 4000V Voltage Applied to Output
In HIGH State (with V
CC
= 0V)
Standard Output 0.5V to V
CC
3-STATE Output 0.5V to +5.5V Current Applied to Output in LOW State (Max) Twice the Rated I
OL
(mA)
Free Air Ambi ent Temperature 0°C to 70°C Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp
1.2 V Min IIN = 18 mA
Diode Voltage
V
OH
Output HIGH 2.4 2.8
VMin
IOH = 3 mA
Voltage 2.0 2.44 IOH = 15 mA
V
OL
Output LOW
0.45 0.55 V Min IOL = 64 mA
Voltage
I
IH
Input HIGH
5.0 µAMaxVIN = 2.7V
Current
I
BVI
Input HIGH Current
7.0 µAMaxVIN = 7.0V (OE, CP)
Breakdown Test
I
BVIT
Input HIGH Current
0.5 mA Max VIN = 5.5V (Dn)
Breakdown (I/O)
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
IID = 1.9 µA
Test All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW
0.6 mA Max
VIN = 0.5V
Current
(OE, CP)
I
OS
Output Short-
100 225 mA Max V
OUT
= 0V
Circuit Current
IIH + Output Leakage Current
70 µAMax
V
OUT
= 2.7V
I
OZH
(Dn)
IIL + Output Leakage
650 µAMax
V
OUT
= 0.5V
I
OZL
Current (Dn)
V
ID
Input Leakage
4.75 V 0.0
IID = 1.9 µA
Test All Other Pins Grounded
I
OD
Output Circuit
3.75 µA0.0
V
IOD
= 150 mV
Leakage Current All Other Pins Grounded
I
ZZ
Bus Drainage Test 100 µA0.0V
OUT
= 5.25V
I
CCH
Power Supply Current 65 mA Max VO = HIGH
I
CCL
Power Supply Current 80 mA Max VO = LOW
I
CCZ
Power Supply Current 80 mA Max VO = HIGH Z
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74F794
AC Electrical Characteristics
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
f
MAX
Maximum Clock Frequency 90 90 MHz
t
PLH
Propagation Delay 2.5 7.0 2.5 8.0
ns
t
PHL
CP to Q
n
2.5 8.0 2.5 9.0
t
PZH
Output Enable Time 2.3 8.5 2.0 9.0
ns
t
PZL
2.0 10.0 2.0 10.5
t
PHZ
Output Disable Time 1.0 7.0 1.0 8.0
ns
t
PLZ
1.0 7.0 1.0 8.0
tS(H) Setup Time, HIGH or LOW 4.0 4.0
ns
tS(L) Bus to Clock 4.0 4.0 tH(H) Hold Time, HIGH or LOW 1.5 1.5
ns
tH(L) Bus to Clock 1.5 1.5 tW(H Clock Pulse Width 5.8 5.8
ns
HIGH or LOW 5.8 5.8
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74F794
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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74F794 8-Bit Register with Readback
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the user.
2. A critical component i n any compon ent of a lif e support device or system whose failu re to perform can be rea­sonably expected to ca use the fa i lure of the life su pp ort device or system, or to affect its safety or effectiveness.
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