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© 2000 Fairchild Semiconductor Corporation DS009593 www.fairchildsemi.com
April 1988
Revised March 2000
74F779 8-Bit Bidirectional Binary Counter with 3-STATE Outputs
74F779
8-Bit Bidirectional Binary Counter with 3-STATE Outputs
General Description
The 74F779 is a fully synchronous 8-stage up/down
counter with multiplexed 3-STATE I/O ports for bus-oriented applications. All control functions (hold, count up,
count down, synchronous load) are controlled by two mode
pins (S
0
, S1). The device als o f eat ure s ca rr y loo kah ead f or
easy cascading. All state changes are initiated by the rising
edge of the clock.
Features
■ Multiplexed 3-STATE I/O ports
■ Built-in lookahead carry capability
■ Count frequency 100 MHz typ
■ Supply current 80 mA typ
■ Available in SOIC (300 mil only)
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbol Connection Diagram
Order Number Package Number Package Description
74F779SC M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F779PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74F779
Unit Loading/Fan Out
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
(Not LL) means S
0
and S1 should never both be LOW level at the same time.
Pin Names Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
I/O0–I/O
7
Data Inputs 0.25/0.33 5 µA/−0.2 mA
Data Outputs 75/15 (12.5) −3 mA/24 mA (20 mA)
S
0
, S
1
Select Inputs 0.25/0.33 5 µA/−0.2 mA
OE
Output Enable Input (Active LOW) 0.25/0.33 5 µA/−0.2 mA
CET
Count Enable Trickle Input (Active LOW) 0.25/0.33 5 µA/−0.2 mA
CP Clock Pulse Input (Active Rising Edge) 0.25/0.33 5 µA/−0.2 mA
TC
Terminal Count Output (Active LOW) 25/12.5 −1 mA/20 mA
S
1
S
0
CET OE CP Function
XXXHXI/O
0
to I/O7 in High Z
X X X L X Flip-Flop Outputs Appear on I/O Lines
LLXH
Parallel Load All Flip-Flops
(Not LL) H X
Hold (TC Held HIGH)
HLLX
Count Up
LHLX
Count Down
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74F779
Logic Diagram
Please note that this d iagram is provided only f or t he understanding of lo gic operations and should not be used to estimat e propagation delays.
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74F779
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditi ons is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in put s .
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V
CC
Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current ((Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
CC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min) 4000V
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
V
OH
Output HIGH 10% V
CC
2.4
VMinIOH = −3 mA
Voltage 5% V
CC
2.7
V
OL
Output LOW 10% V
CC
0.5
VMin
IOL = 20 mA
Voltage 5% V
CC
0.5 IOL = 20 mA
I
IH
Input HIGH Current 5.0 µAMaxVIN = 2.7V (Non-I/O Pins)
I
BVI
Input HIGH Current
7.0 µAMaxVIN = 7.0V (Non-I/O Pins)
Breakdown Test
I
BVIT
Input HIGH Current
0.5 mA Max VIN = 5.5V (I/On)
Breakdown (I/O)
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
IID = 1.9 µA
Test All other pins grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All other pins grounded
I
ZZ
Bus Drainage Test 500 µA0.0V
OUT
= 5.25V
I
IL
Input LOW Current −0.2 mA Max VIN = 0.5V (Non I/O Pins)
IIH + I
OZH
Output Leakage Current 70 µAMaxV
OUT
= 2.7V (I/On)
IIL + I
OZL
Output Leakage Current −200 µAMaxV
OUT
= 0.5V (I/On)
I
OS
Output Short-Circuit Current −60 −150 mA Max V
OUT
= 0V
I
CCH
Power Supply Current 90 mA Max VO = HIGH
I
CCL
Power Supply Current 105 mA Max VO = LOW
I
CCZ
Power Supply Current 110 mA Max VO = HIGH Z
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74F779
AC Electrical Characteristics
AC Operating Requirements
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
f
MAX
Maximum Clock Frequency 100 105 90
t
PLH
Propagation Delay 3.0 5.0 8.0 3.0 8.5
ns
t
PHL
CP to I/O
n
5.0 7.5 11.0 5.0 11.0
t
PLH
Propagation Delay 5.0 7.5 9.0 5.0 10.0
ns
t
PHL
CP to TC
5.0 9.3 10.5 5.0 11.5
t
PLH
Propagation Delay 2.5 3.8 5.5 2.5 6.0
ns
t
PHL
CET to TC
4.56.18.04.58.5
t
PLH
Propagation Delay 3.5 6.5 12.0 3.5 13.0
ns
t
PHL
SN to TC
3.5 7.5 12.0 3.5 13.0
t
PZH
Output Enable Time 3.0 5.0 7.0 3.0 8.0
ns
t
PZL
OE to I/O
n
5.0 8.0 10.0 5.0 10.5
t
PHZ
Output Disable Time 1.0 4.0 6.5 1.0 7.0
ns
t
PLZ
OE to I/O
n
1.03.76.51.07.0
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
UnitsVCC = +5.0V VCC = +5.0V
MinMaxMinMax
tS(H) Setup Time 5.0 5.0
ns
tS(L) I/On to CP 5.0 5.0
tH(H) Hold Time 0.0 0.0
ns
tH(L) I/On to CP 0.0 0.0
tS(H) Setup Time 9.5 10.0
ns
tS(L) Sn to CP 9.5 10.0
tH(H) Hold Time 0.0 0.0
ns
tH(L) Sn to CP 0.0 0.0
tS(H) Setup Time 7.0 7.0
ns
tS(L)
CET to CP
7.0 7.0
tH(H) Hold Time 0.0 0.0
ns
tH(L)
CET to CP
0.0 0.0
tW(H) Clock Pulse Width 4.0 4.0
ns
tW(L) HIGH or LOW 4.0 4.0
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74F779
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M16B
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74F779 8-Bit Bidirectional Binary Counter with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent license s are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided i n the labe li ng, can be re asonably expected to result in a significant injury to the
user.
2. A critical componen t in any com ponent o f a l ife supp ort
device or system whose failu re to perform can b e reasonably expected to c ause th e fa i lure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
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