Datasheet 74F74SJX, 74F74SJ, 74F74SCX, 74F74SC, 74F74PC Datasheet (Fairchild Semiconductor)

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April 1988 Revised July 1999

74F74 Dual D-Type Positive Edge-Triggered Flip-Flop

74F74 Dual D-Type Positive Edge-Trigge red Flip-Flop

General Description

The F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q, Q

) outputs. Information at the input is transferred to the outputs on the positi ve edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to

the outputs until the nex t rising edge of the Clock Pulse input.

Asynchronous Inputs:

LOW input to S

sets Q to HIGH level

LOW input to C

sets Q to LOW level

Clear and Set are independent of clock Simultaneous LOW on C

and S

makes both Q and Q HIGH

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F74

Unit Loading/Fan Out

Tr uth Table

H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial Q

= Previous Q (Q) before LOW-to-HIGH Clock Transition

Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to -HIGH clock trans ition.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pr opagation delays.

Pin Names Description

U.L. Input I

IH/IIL

HIGH/LOW Output IOH/I

D1, D

Data Inputs 1.0/1.0 20 µA/−0.6 mA

, CP

Clock Pulse Inputs (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA

, C

Direct Clear Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA

, S

Direct Set Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA

, Q1, Q2, Q2Outputs 50/33.3 −1 mA/20 mA

Inputs Outputs

CP D Q Q

LHXXHL

HLXXLH

LLXXHH



hH L



lLH

HHLXQ

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74F74

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.

Note 2: Either voltage lim it or curr ent limit is suffic ient to prote ct input s.

DC Electr ic al C h ar acteristi cs

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

(mA)

ESD Last Passing Voltage (Min) 4000V

Free Air Ambient Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% V

2.5 VMin

IOH = −1 mA

Voltage 5% V

2.7 IOH = −1 mA

Output LOW 10% V

0.5 V Min IOL = 20 mA

Voltage

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All Other Pins Grounded

Input LOW Current −0.6

mA Max

VIN = 0.5V (D, CP)

−1.8

VIN = 0.5V (CD, SD)

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

Power Supply Current 10.5 16.0 mA Max

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74F74

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

= 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF

Min Typ Max Min Max

MAX

Maximum Clock Frequency 100 125 100 MHz

PLH

Propagation Delay 3.8 5.3 6.8 3.8 7.8

PHL

CPn to Qn or Q

4.4 6.2 8.0 4.4 9.2

PLH

Propagation Delay 3.2 4.6 6.1 3.2 7.1

PHL

CDn or SDn to Qn or Q

3.5 7.0 9.0 3.5 10.5

Symbol Parameter

TA = +25°CT

= 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V

Min Max Min Max

tS(H) Setup Time, HIGH or LOW 2.0 2.0

tS(L) Dn to CP

3.0 3.0 tH(H) Hold Time, HIGH or LOW 1.0 1.0 tH(L) Dn to CP

1.0 1.0 tW(H) CPn Pulse Width 4.0 4.0

tW(L) HIGH or LOW 5.0 5.0 tW(L)

CDn or SDn Pulse Width

4.0 4.0 ns

LOW

REC

Recovery Time 2.0 2.0 ns CDn or SDn to CP

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74F74

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

Package Number M14A

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

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74F74 Dual D-Type Positive Edge-Triggered Flip-Flop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does no t assume any responsibility for use of an y circuitry d escribed, no c ircuit patent l icenses are impl ied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a sig nificant injury to the user.

2. A critical com ponen t in any com pone nt of a life s upport device or system w hose fa ilure to perform can be r easonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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