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74F564
Octal D-Type Flip-Flop with 3-STATE Outputs
74F564 Octal D-Type Flip-Flop with 3-STATE Outputs
April 1983
Revised August 1999
General Description
The 74F564 is a high-speed, low power octal flip-flop with a
buffered common Clock (CP ) a nd a bu ffered com mo n Ou tput Enable (OE
is sorted in the flip-flops on the LOW-to-HIGH Clock (CP)
transition.
This device is function ally ident ical to th e 74F574 , but has
inverted outputs.
). The information presented to the D inputs
Features
■ Inputs and outputs on opposit e sides of package allow
easy interface with microprocessors
■ Useful as input or output port for microprocessors
■ Functionally identical to 74F574
■ 3-STATE outputs for bus-oriented applications
Ordering Code:
Order Number Package Number Package Description
74F564SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F564PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Logic Symbols
IEEE/IEC
Connection Diagram
© 1999 Fairchild Semiconductor Corporation DS009563 www.fairchildsemi.com
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Unit Loading/Fan Out
74F564
Pin Names Description
D0–D7Data Inputs 1.0/1.0 20 µA/−0.6 mA
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA
OE
O
0–O7
U.L.
HIGH/LOW
3-STATE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
3-STATE Outputs 150/40 (33.3) −3 mA/24 mA (20 mA)
Input I
Output I
IH/IIL
OH/IOL
Functional Description
The 74F564 con sists of eig ht edge- triggered flip-fl ops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Outp ut Enable are com mon to
all flip-flops. The eight flip-flops will stor e the state of their
individual D inputs that meet the setup and hold times
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE
eight flip-flops ar e available at the outputs. When OE
HIGH, the outputs go to th e high imp edance state . Operation of the OE
flops.
input does not affect t he state of the flip-
) LOW, the contents of the
is
Logic Diagram
Function Table
Inputs Internal Outputs
CP D Q O
OE
H H L NC Z Hold
HHH NC Z Hold
H
H
L
L
L H L NC NC No Change in Data
L H H NC NC No Change in Data
H = HIGH Voltage Level Z = High Impedance
L = LOW Voltage Level
X = Immaterial NC = No Change
L H Z Load
H L Z Load
L H H Data Available
H L L Data Available
= LOW-to-HIGH Transitio n
Function
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and shou ld not be used to estimate propagation delays.
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Absolute Maximum Ratings(Note 1) Recommended Operating
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
Pin Potential to Ground Pin −0.5V to +7.0V
V
CC
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
Conditions
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyon d which the device
may be damaged or have its useful life impaired . Functional operation
CC
under these condit ions is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.
(mA)
DC Electrical Characteristics
74F564
Symbol Parameter Min Typ Max Units
V
V
V
V
V
I
IH
I
BVI
I
CEX
V
I
OD
I
IL
I
OZH
I
OZL
I
OS
I
ZZ
I
CCZ
IH
IL
CD
OH
OL
ID
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
Input LOW Voltage 0.8 V Recognized as a LOW Signal
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
Output HIGH 10% V
Voltage 10% V
5% V
5% V
Output LOW
Voltage
10% V
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test All Other Pins Grounded
Output Leakage
Circuit Current All Other Pins Grounded
2.5
CC
2.4 IOH = −3 mA
CC
2.7 IOH = −1 mA
CC
2.7 IOH = −3 mA
CC
CC
0.5 V Min IOL = 24 mA
5.0 µAMaxVIN = 2.7V
7.0 µAMaxVIN = 7.0V
50 µAMaxV
4.75 V 0.0
3.75 µA0.0
Input LOW Current −0.6 mA Max VIN = 0.5V
Output Leakage Current 50 µAMaxV
Output Leakage Current −50 µAMaxV
Output Short-Circuit Current −60 −150 mA Max V
Bus Drainage Test 500 µA0.0VV
Power Supply Current 55 86 mA Max VO = HIGH Z
V
CC
IOH = −1 mA
VMin
OUT
IID = 1.9 µA
V
IOD
OUT
OUT
OUT
OUT
Conditions
= V
CC
= 150 mV
= 2.7V
= 0.5V
= 0V
= 5.25V
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AC Electrical Characteristics
74F564
Symbol Parameter
f
t
t
t
t
t
t
MAX
PLH
PHL
PZH
PZL
PHZ
PLZ
Maximum Clock Frequency 100 70 MHz
Propagation Delay 2.5 5.2 8.5 2.5 8.5
CP to O
n
Output Enable Time 3.0 5.6 9.0 2.5 10.0
Output Disable Time 1.5 3.4 5.5 1.5 6.5
TA = +25°CT
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
2.5 5.9 8.5 2.5 8.5
3.0 6.2 9.0 2.5 10.0
1.5 2.7 5.5 1.5 6.5
AC Operating Requirements
TA = +25°CT
Symbol Parameter
Min Max Min Max
tS(H) Setup Time, HIGH or LOW 2.0 2.0
tS(L) Dn to CP 2.5 2.5
tH(H) Hold Time, HIGH or LOW 2.0 2.0
tH(L) Dn to CP 2.0 2.0
tW(H) CP Pulse Width 5.0 5.0
tW(L) HIGH or LOW 5.0 5.0
= 0°C to +70°C
A
= 0°C to +70°C
A
Units
ns
ns
UnitsVCC = +5.0V VCC = +5.0V
ns
ns
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Physical Dimensions inches (millimeters) unless otherwise noted
74F564
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
74F564 Octal D-Type Flip-Flop with 3-STATE Outputs
Fairchild does not assume any responsibility for us e of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support de vices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significan t injury to the
user.
2. A critical com ponent in any com ponen t of a life supp ort
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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