Page 1
April 1988
Revised August 1999
74F533
Octal Transparent Latch with 3-STATE Outputs
74F533 Octal Transparent Latch with 3-STATE Outputs
General Description
The 74F533 consists of eight latches with 3-STA TE outputs
for bus organized system applications. The flip-flops
appear transparent to the data whe n Latch En able (LE) is
HIGH. When LE is LOW, the data that m eets the setup
times is latched. Data appears on the bus when the Output
Enable (OE
the high impedance st ate. The 74F533 is the same as the
74F373, except that the outputs are inverted.
) is LOW. When OE is HIGH the bus output is in
Features
■ Eight latches in a single package
■ 3-STATE outputs for bus interfacing
■ Inverted version of the 74F373
Ordering Code:
Order Number Package Number Package Description
74F533SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F533SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F533PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Logic Symbols
IEEE/IEC
Connection Diagram
© 1999 Fairchild Semiconductor Corporation DS009548 www.fairchildsemi.com
Page 2
Unit Loading/Fan Out
74F533
Pin Names Description
D0–D
LE Latch Enable Input (Active HIGH) 1.0/1.0 20 µA/−0.6 mA
OE
O
0–O7
Function Table
LE OE
HLH L
HLL H
LLX O
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
XHX Z
Logic Diagram
U.L.
HIGH/LOW
Data Inputs 1.0/1.0 20 µA/−0.6 mA
7
Output Enable Input (Ac tive LOW) 1.0/1.0 20 µA/−0.6 mA
Complementary 3-STATE Outputs 150/40 (33.3) −3 mA/24 mA (20 mA)
Functional Description
Inputs Output
DO
0
The 74F533 contains eight D-typ e latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
the latches are transparent, i.e., a lat ch output will change
state each time its D input cha nges. Whe n LE is LO W, the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LO W transition
of LE. The 3-STATE buffers are controlled by the Out put
Enable (OE
bi-state mode. When OE
impedance mode b ut this does not i nterfere with enter ing
new data into the latches.
inputs enters the latches . In this condition
n
) input. When OE is LOW, the buffers are in the
is HIGH th e bu ffers are i n t h e hi g h
Input I
Output I
IH/IIL
OH/IOL
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and shou ld not be used to estimate propagation delays.
www.fairchildsemi.com 2
Page 3
Absolute Maximum Ratings(Note 1) Recommended Operating
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
Pin Potential to
V
CC
Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
ESD Last Passing Voltage (Min) 4000V
Conditions
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyon d which the device
CC
may be damaged or have its useful life impaired . Functional operation
under these condit ions is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.
(mA)
DC Electrical Characteristics
74F533
Symbol Parameter Min Typ Max Units
V
V
V
V
V
I
I
I
I
V
I
I
I
I
I
I
I
IH
IL
CD
OH
OL
IH
BVI
BVIT
CEX
ID
OD
IL
OZH
OZL
OS
ZZ
CCZ
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
Input LOW Voltage 0.8 V Recognized as a LOW Signal
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
Output HIGH 10% V
Voltage 10% V
5% V
5% V
Output LOW Voltage 10% V
CC
CC
CC
CC
CC
2.5
2.4 IOH = −3 mA
2.7 IOH = −1 mA
2.7 IOH = −3 mA
0.5 V Min IOL = 24 mA
Input HIGH Current 5.0 µAMaxVIN = 2.7V
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown (I/O)
Output HIGH
Leakage Current
Input Leakage
Test All Other Pins Grounded
4.75 V 0.0
Output Leakage
Circuit Current All Other Pins Grounded
7.0 µAMaxVIN = 7.0V
0.5 mA Max VIN = 5.5V
50 µAMaxV
3.75 µA0.0
Input LOW Current −0.6 mA Max VIN = 0.5V
Output Leakage Current 50 µAMaxV
Output Leakage Current −50 µAMaxV
Output Short-Circuit Current −60 −150 mA Max V
Bus Drainage Test 500 µA0.0VV
Power Supply Current 41 61 mA Max VO = HIGH Z
V
CC
IOH = −1 mA
VMin
OUT
IID = 1.9 µA
V
IOD
OUT
OUT
OUT
OUT
Conditions
= V
CC
= 150 mV
= 2.7V
= 0.5V
= 0V
= 5.25V
3 www.fairchildsemi.com
Page 4
AC Electrical Characteristics
74F533
Symbol Parameter
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
Propagation Delay 4.0 6.7 9.0 4.0 12.0 4.0 10.0
Dn to O
n
Propagation Delay 5.0 7.1 11.0 5.0 14.0 5.0 13.0
LE to O
n
Output Enable Time 2.0 5.9 10.0 2.0 12.5 2.0 11.0
Output Disable Time 1.5 3.4 6.5 1.5 8.5 1.5 7.0
TA = +25°CT
VCC = +5.0V VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF CL = 50 pF
Min Typ Max Min Max Min Max
2.54.47.02.59.02.58.0
3.04.77.03.09.03.08.0
2.0 5.6 7.5 2.0 10.5 2.0 8.5
1.52.75.51.57.51.56.5
= −55°C to +125°CTA = 0°C to +70°C
A
AC Operating Requirements
TA = +25°CTA = −55°C to +125°CTA = 0°C to +70°C
Symbol Parameter
tS(H) Setup Time, HIGH or LOW 2.0 2.0 2.0
tS(L) Dn to LE 2.0 2.0 2.0
tH(H) Hold Time, HIGH or LOW 3.0 3.0 3.0
tH(L) Dn to LE 3.0 3.0 3.0
tW(H) LE Pulse Width, HIGH 6.0 6.0 6.0 ns
Min Max Min Max Min Max
Units
ns
ns
ns
ns
UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V
ns
ns
www.fairchildsemi.com 4
Page 5
Physical Dimensions inches (millimeters) unless otherwise noted
74F533
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20B
Package Number M20D
5 www.fairchildsemi.com
Page 6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
74F533 Octal Transparent Latch with 3-STATE Outputs
Fairchild does not assume any responsibility for us e of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significan t injury to the
user.
2. A critical component in any compon ent of a lif e supp ort
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
www.fairchildsemi.com 6
Loading...