Datasheet 74F403ASPC Datasheet (Fairchild Semiconductor)

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74F403A First-In First-Out (FIFO) Buffer Memory

74F403A First-In First-Out (FIFO) Buffer Memor y

January 1989 Revised May 1999

General Description

The 74F403A is an expandable fall-through type highspeed First-In First-Out (FIFO) Buffer Memory optimized for high-speed disk or tape cont rollers a nd commu nication buffer applications. It is organized as 16-words by 4-bits and may be expanded to any number of words or any number of bits in multiples of four. Data may be entered or extracted asynchronously in serial or parallel, allowing economical implementation of buffer memories.

The 74F403A has 3- STATE outputs which provide a dded versatility and is fully compatible with all TTL families.

Features

■ Serial or parallel input

■ Serial or parallel output

■ Expandable without external logic

■ 3-STATE outputs

■ Fully compatible with all TTL families

■ Slim 24-pin package

■ 9403A replacement

■ Guaranteed 4000V minimum ESD prote ction

Ordering Code:

Order Number Package Number Package Description

74F403ASPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram Logic Symbol

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Unit Loading/Fan Out:

See Section 2 for U.L. definitions

74F403A

Names HIGH/LOW

D0 − D3Parallel Data Inputs 1.0/0.667 20 µA/400 µA D

PL Parallel Load Input 1.0/0.667 20 µA/400 µA CPSI Serial Input Clock 1.0/0.667 20 µA/400 µA IES Serial Input Enable 1.0/0.667 20 µA/400 µA TTS Transfer to Stack Input 1.0/0.667 20 µA/400 µA OES Serial Output Enable 1.0/0.667 20 µA/400 µA TOS Transfer Out Serial 1.0/0.667 20 µA/400 µA TOP Transfer Out Parallel 1.0/0.667 20 µA/400 µA MR Master Reset 1.0/0.667 20 µA/400 µA OE Output Enable 1.0/0.667 20 µA/400 µA CPSO Serial Output Clock 1.0/0.667 20 µA/400 µA Q0 − Q3Parallel Data Outputs 285/26.7 5.7 mA/16 mA Q

IRF Input Register Full 20/13.3 −400 µA/8 mA ORE Output Register Empty 20/13.3 −400 µA/8 mA

Description

Serial Data Input 1.0/0.667 20 µA/400 µA

Serial Data Output 285/26.7 5.7 mA/16 mA

U.L.

Input IIH/I

Output IOH/I

Functional Description

As shown in the Block Diag ram the 74F403A consists of three sections:

1. An Input register with parallel and serial data inputs as well as control inp uts and outputs f or input handsha king and expansion.

2. A 4-bit wide, 14-wo rd deep fall- through stack with selfcontained control logic.

3. An Output Register with parallel and serial data outputs as well as control inputs an d outputs for output hand shaking and expansion.

Since these three sections operate asynchronously and almost independently, they will be described separately below.

INPUT REGISTER (DATA ENTR Y)

The Input Register can receive data in either bit-serial or in 4-bit parallel form. It stores this data un til it is sent to the fall-through stack an d genera tes the ne cessary statu s and control signals.

Figure 1 is a conceptual logic diagra m of the in put sectio n. As described later, this 5-bit register is initialized by setting

Block Diagram

the F

flip-flop and rese tting the other flip-flops. The Q out-

put of the last flip- flop (FC) is brought out as the “Input Register Full” output (IRF HIGH.

Parallel Entry— A HIGH on th e PL input loads t he D inputs into the F0-F3 flip-flops and sets the FC flip-flop. This forces the IRF

output LOW indicating that the input register is full. During parallel entry, the CPSI parallel expansion is not bei ng implemented, IES LOW to establish row mastership (see Expansion section).

Serial Entry— Data on the D

, F2, F1, F0, FC shift register on eac h HIGH-to- LOW

the F

transition of the CPSI LOW.

After the fourth clock transition, the four data bits are located in the four flip-flops, F

forcing the IRF

output LOW and inte rnally inhibiting CPSI clock pulses from affecting the regist er, Figure 2 illustrates the final positions in a 74F403A resulting from a 64-bit serial bi t train. B

). After initialization this output is

input must be LOW. If

input is serially entered into

clock input, provided IES an d PL a re

. The FC flip-flop is set,

0-F3

is the first bit, B63 the last bit.

0-D3

must be

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FIGURE 1. Conceptual Input Section

74F403A

FIGURE 2. Final Positions in a 74F403A

Resulting from a 64-Bit Serial Train

Transfer to the Stack— The ou tputs of Flip-Flops F feed the stack. A LOW level o n the TTS input initiates a

“fall-through” action. If the top location of the stack is empty, data is loaded into the stack and the input register is re-initialized. Note that this initialization is postponed until PL is LOW again. Thus, autom ati c FIF O actio n is achieved by connecting the IRF

An RS Flip-Flop (the Request Initialization Flip-Flop shown in Figure 10) in the contr ol section records the fact that data has been transferred to the stack. This prevents multiple entry of the same word into the stack despite the fact

and TTS may still be LOW. The Request Initializa-

the IRF tion Flip-Flop is not cleared until PL goes LOW. Once in the stack, data falls throu gh the stack automatically, pausing only when it is necessary to wait for an empty next location. In the 74F403A as in most modern FIFO designs, the MR input only initializes the stack con trol section and do es not clear the data.

OUTPUT REGISTER (DATA EXTRACTION)

The Output Register receives 4-bit data words from the bottom stack location, stores it and outputs data on a 3STATE 4-bit parallel data bus or on a 3-S TATE serial data bus. The output section generates and receives the necessary status and con trol signals. Figure 3 is a conceptual logic diagram of the output sect ion.

output to the TTS input.

0-F3

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74F403A

FIGURE 3. Conceptual Output Section

Parallel Data Extraction— When the FIFO is empty after a LOW pulse is app lied to MR

) output is LOW. After data has been en ter ed in to th e

(ORE FIFO and has fallen through to the bottom stack location, it

is transferred into th e Output Register provid ed the “Transfer Out Parallel” (TOP) input is HIGH. As a result of the data transfer O RE data outputs (provided the 3-STATE buffer is enabled). TOP can now be used to clock out the next word. When TOP goes LOW, ORE put data has been extracted, bu t the data itself rem ains on the output bus until the next HIGH level at TOP permits the transfer of the next wo rd (if a vailab le) in to the Ou tput Reg ister. During parallel data extraction CPSO TOS should be grounded for single slice operati on or con nected to the appropriate ORE (see Expansion section).

TOP is not edge triggered. Ther efore, if TOP goes HIGH before data is available from the stack, but data does become available befo re TOP goes LOW again , that data will be transferred into the Output Register. However, internal control circuitry prevents the same data from being

goes HIGH, indicating valid da ta on the

, the Output Register Empty

will go LOW indicating that the out-

should be LOW.

for expanded operation

transferred twice. If TOP goes HIGH and retur ns to LOW before data is available fr om the sta ck, ORE indicating that there is no valid data at the outputs.

Serial Data Extraction— When the F IFO is emp ty after a LOW pulse is ap plied to MR

) output is LOW. After data has bee n e nte red into the

(ORE FIFO and has fallen through to the bottom stack location, it is transferred into the Output Register provided TOS is LOW and TOP is HIGH. As a result of the data trans fer

goes HIGH indicating valid data in the register. The 3-

ORE STATE Serial Data Output, Q

and puts the first data bit on the output bus. Data is serially shifted out on the HIGH-to-LOW transition of CPSO prevent false shifting, CPSO word is being loaded into the Output Regist er. The fourth transition empties the shift register, forces ORE LOW and disables the serial output, Q

For serial operation the ORE input, requesting a new word from the stack as soon as the previous one has been shifted out.

, the Output Register empty

, is automatically enabled

should be LOW when the new

output may be tied to the TOS

remains LOW

(refer to Figure 3).

output

. To

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EXPANSION

Vertical Expansion— The 74F403A may be vertically expanded to store more words w ithout external par ts. The interconnection is necessary to form a 46-word by 4-bit FIFO are shown in Figur e 4. Using the same technique, and FIFO of (15n + 1 )-word s by 4- bits can be constr ucted, where n is the number of devices. Note that expansion

does not sacrifice any of the 74F403A’s flexibility for serial/ parallel input and output.

FIGURE 4. A Vertical Expansion Scheme

Horizontal and Vertical Expansion — The 74F403A can be expanded in both the hor izontal and vertical di rections without any external pa rts and wi thou t sacrifici ng any of its

FIFO’s flexibility for serial/parallel input and output. The interconnections necessary to form a 31-word by 16-bit FIFO are shown in Figure 6 . Using the same technique, any FIFO of (15m + 1)-words by (4n)-bits can be constructed, where m is the number of device s in a column and n is the number of devices in a row. Figure 7 and Figure 8 show the timing d iagrams for serial data en try and extraction for the 31-w ord by 16-bit FIFO show n in Figure

6. The final positio n o f dat a af ter serial insertion of 49 6 bi t s into the FIFO array of Figure 6 is shown in Figure 9.

Interlocking Circuitry— Most conventional FIFO designs provide status signal s analogous to IRF ever, when these devices are operated in arrays, variations in unit to unit o perating speed require externa l gating to assure all devices have completed an operation. The

74F403A incorporate s simple but effective “master/slav e” interlocking circuitry to elimin ate the ne ed for ext ernal gating.

In the 74F403A array of Figure 6 devices 1 and 5 are defined as “row masters” and the other devices ar e slaves to the master in their row. No slave in a given row will in itialize its Input Register until it ha s received LOW on its IES input from a row master or a slave of higher priority.

In a similar fash ion, the ORE HIGH until their OES locking scheme ensures that new input data may be accepted by the array when the IRF slave in that row goe s HIGH and that output data for the array may be extracted when the ORE the output row goes HIGH.

The row master is estab lished by connecting its IES to ground while a slave receives its IES output of the next higher prior ity device. When an ar ray of 74F403A FIFOs i s i n iti ali zed wi t h a LOW on t he MR of all devices, the IRF Thus, only the row master receives a LOW on the IES during initialization. Figure 10 is a conceptual logic diagram of the internal circuitry which determines master/slave operation. Whenever MR Latch is set. Whenever TTS ization Flip-Flop will be set. If the Master Latch is HIGH, the Input Register will be immediately initialized and the Request Initialization Flip-Flop reset. If the Mast er Latch is reset, the Input Register is not initialized until IES LOW. In array operation, activ ating the TTS ple input register i nitialization from the row master to the last slave.

A similar operation takes place for the output register. Either a TOS ation and sets the ORE Latch is set, the last Output Register Flip-Fl op is set and ORE put will be LOW until an OES

or TOP input initiates a load-from-stack oper-

goes HIGH. If the Master Latch is reset, the ORE out-

outputs of slaves will not go

inputs have gone HIGH.This inter-

outputs of all devices will be HIGH .

and IES are LOW, the Master

goes LOW the Request Initial-

Request Flip-Flop. If the Master

input is received.

and ORE. How-

output of the final of the final slave in

input

input from the IRF

inputs

input

goes

initiates a rip-

74F403A

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74F403A

FIGURE 5. A Horizontal Expansion Scheme

FIGURE 6. A 31 x 16 FIFO Array

GRAPHIC 00953610

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FIGURE 7. Serial Data Entry for Array of Figure 6

74F403A

FIGURE 8. Serial Data Extraction for Array of Figure 6

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74F403A

FIGURE 9. Final Position of a 496-Bit Serial Input

FIGURE 10. Conceptual Diagram, Interlocking Circuitry

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Absolute Maximum Ratings(Note 1) Recommended Operating

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +175°C

Pin Potential to Ground Pin −0.5V to +7.0V

Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

In HIGH State (with V

= 0V) Standard Output −0.5V to V 3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

ESD Last Pa ssing Voltage (Min) 4000V

Conditions

Free Air Ambient Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Note 1: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation under these condit ions is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protec t in puts.

(mA)

DC Electrical Characteristics

74F403A

Symbol Parameter Min T ype Max Units

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.5 V Min IIN = −18 mA

Output HIGH 10% VCC2.5

Voltage

Output LOW

Voltage

Input HIGH Current 20 µAMaxVIN = 2.7V

Input HIGH Current

BVI

Breakdown Test

Input LOW Current −0.4 mA Max VIN = 0.5V

Output Leakage Current 50 µAMaxV

OZH

Output Leakage Current −50 µAMaxV

OZL

Output Short-Circuit Current −20 −130 mA Max V

Output HIGH Leakage Current 250 µAMaxV

CEX

Power Supply Current 170 mA Max V0 = LOW

CCL

10% V 5% VCC2.7 IOH = −400 µA (IRF, ORE)

5% VCC2.7 IOH = −5.7 mA (Qn, Qs) 10% V 10% V

2.5 IOH = −5.7 mA (Qn, Qs)

CC CC

0.5

0.5 IOL = 16 mA (Qn, Qs)

100 µAMaxVIN = 7.0V

IOH = −400 µA (IRF, ORE)

VMin

IOL = 8 mA (IRF, ORE)

OUT OUT OUT OUT

= 2.7V = 0.5V = 0V = V

Conditions

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AC Electrical Characteristics

74F403A

Symbol Parameter

t t

t t t t

t t

PHL

PLH

PLH PHL

PHL

PLH

PHL

PLH

PHL

PZH PZL PHZ PLZ PZH PZL

PHZ PLZ

Propagation Delay, Negative-Going

CPSI to IRF Output Propagation Delay, Negative-Going

TTS to IRF Propagation Delay, 8.5 17.0 7.5 18.5 Negative-Going 8.0 14.5 7.0 15.5 CPSO to QS Output Propagation Delay, 10.0 18.0 9.0 20.0 Positive-Going 8.5 15.5 8.0 16.5 TOP to Outputs Q0-Q

Propagation Delay, Negative-Going

CPSO to ORE Propagation Delay, Negative-Going

TOP to ORE Propagation Delay, Positive-Going TOP or ORE Propagation Delay, Negative-Going TOS to Positive Going ORE Propagation Delay, Positive-Going

PL to Negative-Going IRF Propagation Delay, Negative-Going

PL to Positive-Going IRF Propagation Delay,

OES to ORE Propagation Delay, Positive-Going IES to Positive-Going IRF Propagation Delay, MR to IRF Propagation Delay, MR to ORE Propagation Delay, 2.5 6.5 2.0 8.0 OE to Q0, Q1, Q2, Q

Propagation Delay, 2.5 6.5 2.0 8.0 OE to Q0, Q1, Q2, Q

Propagation Delay, 5.5 12.0 5.0 15.0 Negative-Going 5.5 14.0 5.0 15.0 OES to Q

Propagation Delay, 5.5 12.0 5.0 14.0 Negative-Going 5.5 14.5 5.0 16.0 OES to Q

TA = +25°CT

VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF

= 0° to +70°C

Units

Figure

Number

Min Max Min Max

7.5 14.0 7.0 15.0 Figure 11

Figure 12

11.0 20.5 10.0 22.5

Figure 13

Figure 14

ns Figure 15t

9.5 17.5 9.0 19.0 ns

Figure 13 Figure 14

8.0 15.0 7.5 16.5

ns Figure 15

12.5 22.0 11.5 25.0

12.5 22.0 11.0 25.0 ns

Figure 13 Figure 14

7.0 13.0 6.5 14.0 Figure 17

Figure 18

9.5 17.0 8.5 19.5

10.0 18.0 9.0 20.5 nsApostatize-Going

8.5 15.5 7.5 17.5 ns Figure 18

8.0 15.0 7.5 17.0 ns

9.0 16.0 8.0 17.5 ns

2.5 7.5 2.0 8.5

2.5 7.5 2.0 8.0

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AC Electrical Characteristics (Continued)

74F403A

TA = +25°CT

Symbol Parameter

t t t t

PZH PZL DFT AP

Turn On Time 8.5 21.0 8.0 24.0 TOS to Q

Fall Through Time 45.0 80.0 35.0 95.0 ns Figure 16 Parallel Appearance Time, ORE to Q0-Q Serial Appearance Time, ORE to Q

VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF

Min Max Min Max

8.5 20.0 8.0 21.0

−10.0 −1.0 −10.0 −1.0

−10.0 2.0 −10.0 20

AC Operating Requirements

TA = +25°CT

Symbol Parameter

tS(H) Set-up Time HIGH or LOW 1.0 1.0 tS(L)

tH(H) Hold Time, HIGH or LOW 3.5 3.5 tH(L)

tS(L) Set-up Time, LOW

tS(H) Set-up Time, HIGH or LOW 0 0 tS(L) Parallel Inputs to PL 0 0 tH(H) Hold Time, HIGH or LOW 2.0 2.5 tH(L) Parallel Inputs to PL 2.0 2.5

tW(H) CPSI Pulse Width 5.0 6.0 tW(L) HIGH or LOW 3.0 5.0 tW(H) PL Pulse Width, HIGH

tW(L) TTS Pulse Width, LOW

tW(L) MR Pulse Width, LOW 3.5 4.0 tW(H) TOP Pulse Width 4.5 5.5 tW(L) HIGH or LOW 3.5 4.0

tW(H) CPSO Pulse Width 4.5 5.5 tW(L) HIGH or LOW 3.0 4.0 t

REC

DS to Negative CPSI

DS to CPSI

TTS to IRF Serial or Parallel Mode

Negative-Going ORE to Negative-Going TOS

Negative-Going IES to CPSI

Negative-Going TTS to CPSI

Serial or Parallel Mode

Recovery Time MR to Any Input

VCC = +5.0V VCC = +5.0V

Min Max Min Max

1.0 1.0

3.5 3.5

00ns

3.0 4.0 ns Figure 12

14.0 15.5 ns Figure 12

4.0 5.0 ns

3.5 4.0 ns

5.0 5.5 ns Figure 16

= 0° to +70°C

= 0°C to +70°C

Units

Figure

Number

Figure

Number

Figure 11

Figure 12

Figure 11 Figure 12 Figure 17 Figure 18

Figure 13 Figure 14

Figure 11

Figure 12 Figure 17

Figure 18 Figure 11

Figure 12 Figure 13 Figure 14

ns Figure 16

ns Figure 15

Figure 13

Figure 14

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Timing Waveforms

74F403A

Conditions: stack not full, IES, PL LOW

Conditions: stack not full, IES HIGH when initiated, PL LOW

FIGURE 11. Serial Input, Unexpanded or Master Operation

FIGURE 12. Serial Input, Expanded Slave Operation

Conditions: data in stack, TOP HIGH, IES LOW when initiated, OES LOW

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FIGURE 13. Serial Output, Unexpanded or Master Operation

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Timing Waveforms (Continued)

74F403A

Conditions: data in stack, TOP HIGH, IES HIGH when initiated

Conditions: IES LOW when initiated, OE, CPSO LOW; data available in stack

FIGURE 15. Parallel Output, 4-Bit Word or Master in Parallel Expansion

FIGURE 14. Serial Output, Slave Operation

Conditions: TTS connected to IRF, TOS connected to O RE, IES, OES, OE, CPSO LOW, TOP HIGH

FIGURE 16. Fall Through Time

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Timing Waveforms (Continued)

74F403A

Conditions: stack not full, IES LOW when initialized

NOTE A:TTS NOTE B: If stack is full, IRF

normally connected to IRF.

will stay LOW.

FIGURE 17. Parallel Load Mode, 4-Bit Word (Unexpanded) or Master in Parallel Expansion

Conditions: stack not full, device initialize d (N ote 3) with IES HIGH

FIGURE 18. Parallel Load, Slave Mode

Note 3: Initializati on requires a master re s et to oc c ur after power has been applied.

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Physical Dimensions inches (millimeters) unless otherwise noted

74F403A First-In First-Out (FIFO) Buffer Memor y

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or system s are de vices o r syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provide d in the l ab eling , can be re asonably expected to result in a significa nt injury to the user.

Package Number N24C

2. A critical component in any component of a life support device or system whose failure to perform can be r easonably expected to cau se th e f ai lur e o f the lif e sup por t device or system, or to affect its safety or effectiveness.

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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.