Datasheet 74F402PC Datasheet (Fairchild Semiconductor)

74F402
Serial Data Polynomial Generator/Checker

74F402 Serial Data Polynomial Generator/Checker

April 1988
Revised August 1999

General Description

The 74F402 expandable Serial Data Polynomial generator/
checker is an expandable versio n of the 74F401. It pro­vides an advanced tool for th e implem entation of th e most
widely used error detection scheme in serial dig ital han­dling systems. A 4-bit control input sel ects one-of-six gen­erator polynomials. The list of polynomials includes CRC­16, CRC-CCITT and Ethernet, as well as three other

standard polynomials (56
Individual clear and pre set inputs are provided for floppy
disk and other applications. The Error output indicates
whether or not a transmission error has occurred. The
CWG Control input inhibits feedback during check word
transmission. The 74F402 is compatible with FAST
devices and with all TTL families.

th

order, 48th order, 32nd order).

Features

■ Guaranteed 30 MHz data rate

■ Six selectable polynomials

■ Other polynomials available

■ Separate preset and clear controls

■ Expandable

■ Automatic right justification

■ Error output open collector

■ Typical applications: Floppy and othe r disk stora ge sys-

tems Digital cassette and cartridge systems Data com­munication systems

Ordering Code:

Order Number Package Number Package Description

74F402PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Logic Symbol Connection Diagram

FAST is a regist ered trademark of Fair c hild Semiconductor Corporation.
Ethernet is a registe red trademark of Xerox C orporation.

© 1999 Fairchild Semiconductor Corporation DS009535 www.fairchildsemi.com

Unit Loading/Fan Out

74F402

Note 1: Open Collector

Pin Names Description

S0–S

CWG Check Word Generate Input 1.0/0.67 20 µA/−0.4 mA
D/CW Serial Data/Check Word 285(100)/13.3(6.7) −5.7 mA(−2 mA)/8 mA (4 mA)
D Data Input 1.0/0.67 20 µA/−0.4 mA

ER
RO Register Output 285(100)/13.3(6.7) −5.7 mA(−2 mA)/8 mA (4 mA)
CP Clock Pulse 1.0/0.67 20 µA/−0.4 mA
SEI Serial Expansion Input 1.0/0.67 20 µA/−0.4 mA
RFB Register Feedback 1.0/0.67 20 µA/−0.4 mA
MR Master Reset 1.0/0.67 20 µA/−0.4 mA
P

Polynomial Select Inputs 1.0/0.67 20 µA/−0.4 mA

3

Error Output (Note 1) /26.7(13.3) (Note 1) /16 mA (8 mA)

Preset 1.0/0.67 20 µA/−0.4 mA

Functional Description

The 74F402 Serial Data Polynomial Generato r/Checker is
an expandable 16-bit programmable device which oper­ates on serial data streams and provides a means of
detecting transmission er rors. Cyclic encod ing and decod­ing schemes for err or detection are based on poly nomial
manipulation in m odulo arithmetic . For encoding , the data
stream (message polynomial) is divided by a selected poly­nomial. This division results in a remainder (or residue)
which is appended t o th e m essa ge a s che ck bi t s. Fo r e rro r
checking, the bit st ream containing both data and check
bits is d ivided by the same selected polynomial. If there are
no detectable errors, th is division results in a zero remain ­der. Although it is possible to choose many generating
polynomials of a given de gre e, stan dar ds exist tha t spe cify
a small number of usefu l polynomials. The 7 4F402 imple­ments the polynomials listed in Table 1 by applying the
appropriate logic levels to the select pins S

The 74F402 consists of a 16-bit register, a Read Only
Memory (ROM) and associated control circuitry as show n
in the Block Diagram. The polynomial control code pre­sented at inputs S

selecting the desir ed polynom ial o r part of a p olyno mia l by
establishing shift mode operation on the register with
Exclusive OR (XOR) gates at appropriate inputs. To gener­ate the check bits, the data stre am is entered via the Data
Inputs (D), using the LOW-to-HIGH transit ion of the Clock
Input (CP). This data is gated with the most significant
Register Output (RO) via the Register Feedback Input
(RFB), and controls the XOR gates. The Check Word Gen-

, S1, S2 and S3 is decoded by the ROM,

0

, S1, S2 and S3.

0

U.L.

HIGH/LOW

erate (CWG) mu st be held HIGH while t he data is being
entered. After the last data bit is entered, the CWG is
brought LOW and the check b its are shift ed ou t of the reg­ister(s) and appended to the data bits (no external gating is
needed).

To check an incoming messa ge for errors, both the data
and check bits are enter ed through the D Input with the
CWG Input held HIGH. The Error Output becom es valid
after the last check bit has been entered into the ’F402 by a
LOW-to-HIGH transition of CP, with the exception of the
Ethernet polynomial (see Applications paragraph). If no
detectable errors ha ve occurred during the data transmis­sion, the resultant internal register bits are all LOW and the
Error Output (ER
occurred, ER
to-HIGH transition o f CP or until th e device has b een pre­set or reset.

A HIGH on the Master Reset Input (MR) asynchronous ly
clears the entire register. A LOW on the Preset Input (P
asynchronously sets the enti re register with the exception
of:

1. The Ethernet residue se lection, in which the regist ers
containing the non-zero res idue are cleared;

2. The 56th order polynomial, in which the 8 least signifi­cant register bits of the least significant device are
cleared; and,

3. Register S = 0, in which all bits are cleared.

) is HIGH. If a detectable error has

is LOW. ER remains valid until the next LOW-

Input I

Output I

IH/IIL
OH/IOL

)

www.fairchildsemi.com 2

TABLE 1.

Hex

S

3

Select Code

S

S

2

S

1

0

Polynomial Remarks

0LLLL0 S = 0
CHHLLX
DHHLHX
EHHHLX
FHHHHX
7LHHHX
BHLHHX
3LLHHX
2LLHLX
4LHLLX
8HLLLX
5LHLHX

32+X26+X23+X22+X16
12+X11+X10+X8+X7+X5+X4+X2
32+X31+X27+X26+X25+X19+X16
15+X13+X12+X11+X9+X7+X6+X5+X4+X2
16+X15+X2
16+X12+X5
56+X55+X49+X45+X41
39+X38+X37+X36+X31
22+X19+X17+X16+X15+X14+X12+X11+X9
5

+X+1

48+X36+X35+

+1 CRC-16
+1 CRC-CCITT

+ Ethernet

+X+1 Polynomial

+ Ethernet

+
+ 56th

9HLLHX23+X21+ 48th
1LLLHX
6LHHLX
AHLHLX

15+X13+X8+X2
32+X23+X21
11+X2

+1Order

+ 32nd

+1Order

Block Diagram

74F402

+X+1 Residue

+ Order

3 www.fairchildsemi.com

P

74F402

Select Code

0 0000100S = 0

P

3

2

C 1111101Ethernet
D 1111101Polynomial
E 0000000Ethernet
F 0000010Residue

7 1111100CRC-16

B 1111100CRC-CCITT

3 1111100
2 111110056th
4 1111100Order
8 0011100
5 111110048th
9 1111100Order
1 1111100
6 111110032nd

A 1111100Order

Applications

In addition to polynomial selection there are four other
capabilities provided for in the 74F402 ROM. The first is set
or clear selectability. The sixteen internal registers have the
capability to be either set or cleared when P
LOW. This set or clear capability is done in four groups of 4
(see Table 2, P

). The second ROM capability (C0) is in

0–P3

determining the po larity of the check word. A s is the case
with the Ethernet polynomial the check word can be
inverted when it is appended to the data stream or as is the
case with the other polynom ials, the residue is appended
with no inversion. Thirdly, the ROM contains a bit (C

which is used to select th e RFB input instead of the SEI
input to be fed into the LSB. This is used whe n th e p ol yno ­mial selected is actually a residu e (least signific ant) stored
in the ROM which indicates whether the selected locatio n
is a polynomia l o r a re si due . If the l a tter, then it in hi bits th e
RFB input.

As mentioned previously, upon a successful data transmis­sion, the CRC register has a zero residue. There is an
exception to this, however, with respect to the Ethernet
polynomial. This polynom ial, upo n a successful dat a trans­mission, has a non-zero residue in the CRC register (C7 04
DD 7B)

. In order to provide a no-error indication, two

16

ROM locations have b een preloaded with the residue so
that by selecting these loca tions and clocking the device
one additional time, after the last check bit has been
entered, will result in zeroing the CRC register. In this man­ner a no-error indication is achieved.

With the present mix of polynomials, the largest is 56
order requiring four device s while the smallest is 16th order

requiring just one de vice. In order to acc ommodate multi­plexing between h igh orde r pol ynomi als (X 16

lower order polynomials, a location of all zeros is provided.

is brought

th

order) and

P

1

TABLE 2.

P

C

C

C

0

2

1

0

Polynomial

This allows the user to choose a lower or der polynomial
even if the system is configured for a higher order one.

The 74F402 expandable CRC generator checker contains
6 popular CRC polynomials, 2-16

th

Order and 1-56th Order. The application diagram

48
shows the 74F402 connecte d for a 56

th

Order, 2-32nd Order, 1-

th

Order polynomial.
Also shown are the inp ut patterns for other polynomials.
When the 74F402 is used with a gated clock, d isablin g the
clock in a HIGH state will ensure no errone ous clocking
occurs when the clock is re-enabl ed. Preset and Master

)

1

Reset are asynchronou s inputs p resettin g the re giste r to S
or clearing to 1s re spectively (note Ethernet resi due and

th

Order select code 8, LSB, are exceptions to th is).

56
To generate a CRC, the pattern for the selected polynomial

is applied to the S inputs, t he register is preset or cleared
as required, clock is enabled, CW G is set HIGH, data is
applied to D input, output data is on D/CW. When the last
data bit has been enter ed, CWG is set L O W an d th e re gi s­ter is clocked for n bits (where n is the ord er of the polyn o­mial). The clock may now be stopped if desired (holding
CWG LOW and clocki ng t he re gi ste r w ill ou tpu t ze ros from
D/CW after the residue has been shifted out).

To check a CRC, the pattern for the selected polynomial is
applied to the S inputs, the re gister is preset or cleared as
required, clock is enabled, CWG is set HIGH, the data
stream including the CRC is applied to D input. When the
last bit of the CRC has been entered, the ER
checked: HIGH = error free data , LOW = cor rupt data. T he

th

clock may now be stopped if desired.
To implement polynomials of lower order than 56

the number of packa ges required for the order of pol yno­mial and apply the pattern for the selected polynomial to
the S inputs (0000 on S inputs disab les the pac kage from
the feedback chain).

output is

th

, select

www.fairchildsemi.com 4

74F402

5 www.fairchildsemi.com

Absolute Maximum Ratings(Note 2) Recommended Operating

Storage Temperature −65°C to +150°C

74F402

Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C

Pin Potential to Ground Pin −0.5V to +7.0V

V

CC

Input Voltage (Note 3) −0.5V to +7.0V
Input Current (Note 3) −30 mA to +5.0 mA
Voltage Applied to Output

in HIGH State (with V

CC

= 0V)
Standard Output −0.5V to V
3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

OL

Conditions

Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V

Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation

CC

under these conditi ons is not implied.
Note 3: Either voltage limit or curren t limit is sufficient to protect in put s .

(mA)

DC Electrical Characteristics

Symbol Parameter Min Typ Max Units

V
V
V
V

V

I

I

I

V

I

I
I

I

I

IH
IL
CD
OH

OL

IH

BVI

CEX

ID

OD

IL
OS
OHC

CC

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
Input LOW Voltage 0.8 V Recognized as a LOW Signal
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
Output HIGH 10% V
Voltage 5% V
Output LOW 10% V
Voltage 10% V
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test All Other Pins Grounded
Output Leakage
Circuit Current All Other Pins Grounded
Input LOW Current −0.4 mA Max VIN = 0.5V
Output Short-Circuit Current −20 −130 mA Max V
Open Collector, Output
OFF Leakage Test
Power Supply Current 110 165 mA Max

2.4

CC

2.7 IOH = −5.7 mA (RO, D/CW)

CC
CC
CC

4.75 V 0.0

0.5

0.5 IOL = 8 mA (D/CW, RO)

5.0 µAMaxVIN = 2.7V

7.0 µAMaxVIN = 7.0V

50 µAMaxV

3.75 µA0.0

250 µAMin

V

CC

VMin

IOH = −5.7 mA (RO, D/CW)

IOL = 16 mA (ER)

IID = 1.9 µA

V

V

Conditions

= V

OUT

CC

= 150 mV

IOD

= 0V (D/CW, RO)

OUT

= VCC (ER)

OUT

www.fairchildsemi.com 6

AC Electrical Characteristics

Symbol Parameter

f
t
t
t
t
t
t
t
t
t

t

t
t
t

t

t
t
t
t
t
t

MAX
PLH
PHL
PLH
PHL
PLH
PHL

PLH
PHL
PLH

PLH

PLH
PHL
PHL

PLH

PLH
PHL
PLH
PHL
PLH
PHL

Maximum Clock Frequency 30 45 30 30 MHz
Propagation Delay 8.5 15.0 19.0 7.5 26.5 7.5 21.0
CP to D/CW 10.5 18.0 23.0 9.5 26.5 9.5 25.0
Propagation Delay 8.0 13.5 17.0 7.0 26.0 7.0 19.0
CP to RO 8.0 14.0 18.0 7.0 22.5 7.0 20.0
Propagation Delay 15.5 26.0 33.0 14.0 38.5 14.0 35.0

CP to ER
Propagation Delay 11.0 18.5 23.5 10.0 31.0 10.0 25.5
P to D/CW 11.5 19.5 24.5 10.5 32.0 10.5 26.5
Propagation Delay

P to RO
Propagation Delay

P to ER
Propagation Delay 10.5 18.0 23.0 9.5 29.0 9.5 25.5
MR to D/CW 11.0 19.0 24.0 10.0 28.5 10.0 26.0
Propagation Delay
MR to RO
Propagation Delay

MR to ER
Propagation Delay 6.0 10.5 13.5 5.0 19.5 5.0 15.0
D to D/CW 7.5 12.0 16.0 6.5 20.0 6.5 18.0
Propagation Delay 6.5 11.0 14.0 5.5 21.5 5.5 15.5
CWG to D/CW 7.0 12.0 15.5 6.0 21.5 6.0 17.5
Propagation Delay 11.5 19.5 24.5 9.0 29.0 10.5 26.5
Sn to D/CW 9.5 16.0 20.0 8 .5 25.0 8.5 22.0

TA = +25°CT

VCC = +5.0V VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

= −55°C to +125°CTA = 0°C to +70°C

A

Units

Min Typ Max Min Max Min Max

8.5 14.5 18.5 7.5 23.5 7.5 20.5

9.5 16.0 20.5 8.5 31.5 8.5 22.5 ns

10.0 17.0 21.5 9.0 26.0 9.0 23.5 ns

9.0 15.5 19.5 8.0 23.5 8.0 21.5 ns

16.5 28.0 35.5 14.5 39.0 14.5 37.5 ns

74F402

ns

ns

ns

ns

ns

ns

ns

ns

7 www.fairchildsemi.com

AC Operating Requirements

74F402

Symbol Parameter

tS(H) Setup Time, HIGH or LOW 4.5 6.0 5.0
tS(L) SEI to CP 4.5 6.0 5.0
tH(H) Hold Time, HIGH or LOW 0 1.0 0
tH(L) SEI to CP 0 1.0 0
tS(H) Setup Time, HIGH or LOW 11.0 14.0 12.5
tS(L) RFB to CP 11.0 14.0 12.5
tH(H) Hold Time, HIGH or LOW 0 0 0
tH(L) RFB to CP 0 0 0
tS(H) Setup Time, HIGH or LOW 13.5 16.0 15.0
tS(L) S1 to CP 13.0 15.5 14.5
tH(H) Hold Time, HIGH or LOW 0 0 0
tH(L) S1 to CP 0 0 0
tS(H) Setup Time, HIGH or LOW 9.0 11.5 10.0
tS(L) D to CP 9.0 11.5 10.0
tH(H) Hold Time, HIGH or LOW 0 0 0
tH(L) D to CP 0 0 0
tS(H) Setup Time, HIGH or LOW 7.0 9.0 8.0
tS(L) CWG to CP 5.5 8.0 6.5
tH(H) Hold Time, HIGH or LOW 0 0 0
tH(L) CWG to CP 0 0 0
tW(H) Clock Pulse Width 4.0 7.0 4.5
tW(L) HIGH or LOW 4.0 5.0 4.5
tW(H) MR Pulse Width, HIGH 4.0 7.0 4.5 ns

tW(L) P Pulse Width, LOW 4.0 5.0 4.5 ns
t

t

REC

REC

Recovery Time
MR to CP
Recovery Time

P to CP

TA = +25°CTA = −55°C to +125°CTA = 0°C to +70°C

Min Max Min Max Min Max

3.0 4.0 3.5

5.0 6.5 6.0

UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V

ns

ns

ns

ns

ns

ns

ns

www.fairchildsemi.com 8

Physical Dimensions inches (millimeters) unless otherwise noted

74F402 Serial Data Polynomial Generator/Checker

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent license s are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the labe l ing, can be re a­sonably expected to result in a significant injury to the
user.

Package Number N16E

2. A critical componen t in any com ponen t of a life s upport
device or system whose failu re to perform can b e rea­sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

9 www.fairchildsemi.com