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© 1999 Fairchild Semiconductor Corporation DS009533 www.fairchildsemi.com
April 1988
Revised August 1999
74F398 • 74F399 Quad 2-Port Register
74F398 • 74F399
Quad 2-Port Register
General Description
The 74F398 and 7 4F399 are the logical equi valents of a
quad 2-input multiplexe r feeding into four edge-triggered
flip-flops. A common Select input determines which of the
two 4-bit words is accep ted. The selected da ta enters the
flip-flops on the risin g ed ge of th e cl ock . Th e 74 F3 99 i s t he
16-pin version of the 74F398, with only the Q outputs of the
flip-flops available.
Features
■ Select inputs from two data sources
■ Fully positive edge-triggered operation
■ Both true and complement outputs—74F398
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.
Connection Diagrams
74F398 74F399
Order Number Package Number Package Description
74F398SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74F398PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74F399SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74F399SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F399PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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74F398 • 74F399
Logic Symbols
74F398
74F399
IEEE/IEC
74F398
74F399
Unit Loading/Fan Out
Pin Names Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
S Common Select Input 1.0/1.0 20 µA/−0.6 mA
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA
I
0a–I0d
Data Inputs from Source 0 1.0/1.0 20 µA/−0.6 mA
I
1a–I1d
Data Inputs from Source 1 1.0/1.0 20 µA/−0.6 mA
Q
a–Qd
Register True Outputs 50/33.3 −1 mA/20 mA
Q
a–Qd
Register Complementary Outputs (74F398) 50/33.3 −1 mA/20 mA
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74F398 • 74F399
Functional Description
The 74F398 and 74F399 are high-speed quad 2-port registers. They select four bits of data from either of two sources
(Ports) under control of a com mon Select input (S). The
selected data is transferred to a 4-b it output register synchronous with the LOW-to-HIGH transition of the Clock
input (CP). The 4-bit D-typ e output register is fully edgetriggered. The Data inputs (I
0x
, I1x) and Select input (S )
must be stable only a setup time prior to and hold time after
the LOW-to-HIGH transition of the Clock input for predictable operation. The 74F398 has both Q and Q
outputs.
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH
clock transition
I = LOW Voltage Level one setup tim e prior to the LOW-to-HIGH
clock transition
X = Immaterial
Note 1: 74F398 only
Logic Diagram
*F398 Only
Please note that this d iagram is provided only f or t he understanding of lo gic operations and should not be used to estimat e propagation delays.
Inputs Outputs
SI
0
I
1
QQ
(Note 1)
IIXLH
IhXHL
hX I LH
hX hHL
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74F398 • 74F399
Absolute Maximum Ratings(Note 2) Recommended Operating
Conditions
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditi ons is not implied.
Note 3: Either voltage limit or curren t limit is sufficient to protect in put s .
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V
CC
Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 3) −0.5V to +7.0V
Input Current (Note 3) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
CC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
ESD Last Passing Voltage
(Min)—74F399 4000V
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
V
OH
Output HIGH 10% V
CC
2.5
VMin
IOH = −1 mA
Voltage 5% V
CC
2.7 IOH = −1 mA
V
OL
Output LOW 10% V
CC
0.5 V Min IOL = 20 mA
Voltage
I
IH
Input HIGH Current 5.0 µAMaxVIN = 2.7V
I
BVI
Input HIGH Current
7.0 µAMaxVIN = 7.0V
Breakdown Test
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
IID = 1.9 µA
Test All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current −0.6 mA Max VIN = 0.5V
I
OS
Output Short-Circuit Current −60 −150 mA Max V
OUT
= 0V
I
CCH
Power Supply Current (74F398) 25 38 mA Max VO = HIGH
I
CCL
Power Supply Current (74F398) 25 38 mA Max VO = LOW
I
CCH
Power Supply Current (74F399) 22 34 mA Max VO = HIGH
I
CCL
Power Supply Current (74F399) 22 34 mA Max VO = LOW
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74F398 • 74F399
AC Electrical Characteristics
Note 4: 74F398 3.3 ns
AC Operating Requirements
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
f
MAX
Input Clock Frequency 100 140 100 MHz
t
PLH
Propagation Delay 3.0
(Note 4)
5.7 7.5 3.0 8.5
ns
t
PHL
CP to Q or Q 3.0 6.8 9.0 3.0 10.0
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
UnitsVCC = +5.0V VCC = +5.0V
Min Max Min Max
tS(H) Setup Time, HIGH or LOW 3.0 3.0
ns
tS(L) In to CP 3.0 3 .0
tH(H) Hold Time, HIGH or LOW 1.0 1.0
tH(L) In to CP 1.0 1 .0
tS(H) Setup Time, HIGH or LOW 7.5 8.5
ns
tS(L) S to CP (F398) 7.5 8.5
tS(H) Setup Time, HIGH or LOW 7.5 8.5
tS(L) S to CP (F399) 7.5 8.5
tH(H) Hold Time, HIGH or LOW 0 0
tH(L) S to CP 0 0
tW(H) CP Pulse Width 4.0 4.0
ns
tW(L) HIGH or LOW 5.0 5.0
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74F398 • 74F399
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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74F398 • 74F399
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
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74F398 • 74F399 Quad 2-Port Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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