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© 1999 Fairchild Semiconductor Corporation DS009528 www.fairchildsemi.com
May 1988
Revised August 1999
74F381 4-Bit Arithmetic Logic Unit
74F381
4-Bit Arithmetic Logic Unit
General Description
The 74F381 p er f or ms t h re e ar it h me ti c an d th r ee lo gic operations on two 4-bit wo rds, A and B. Two additional sel ect
input codes force the function outputs LOW or HIGH. Carry
propagate and gener ate outputs are provided for use w ith
the 74F182 carry lookahead generator for high-speed
expansion to longer word lengths. For ripple expansion,
refer to the 74F382 ALU data sheet.
Features
■ Low input loading minimizes drive requirements
■ Performs six arithmetic and logic functions
■ Selectable LOW (clear) and HIGH (preset) functions
■ Carry generate and propagate outputs for use with carry
lookahead generator
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F381SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F381SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F381PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74F381
Unit Loading/Fan Out
Functional Description
Signals applied to the Select inputs S0–S2 determine the
mode of operation, as indicated in the Function Select
Table. An extensive listing of input and output levels is
shown in the Truth Table. The circuit perform s the arithmetic functions for eit her active HIGH or active LOW o perands, with output levels in the same convention. In the
Subtract operating m odes, it is necessa ry to force a carry
(HIGH for active HIGH operands, LOW for active LOW
operands) into the C
n
input of the least significant package.
The Carry Generate (G
) and Carry Propa gate (P) outputs
supply input signals to the 74F1 82 carry lookahe ad generator for expansion to lo nger word leng th, as shown in Figure 2. Note that an 74F382 ALU is used for the most
significant package. Typical delays for Figure 2 are given in
Figure 1.
Function Select Table
H = HIGH Voltage Level
L = LOW Voltage Level
FIGURE 1. 16-Bit Delay Tabulation
FIGURE 2. 16-Bit Lookahead Carry ALU Expansion
Pin Names Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
A0–A
3
A Operand Inputs 1.0/3.0 20 µA/−1.8 mA
B
0–B3
B Operand Inputs 1.0/3.0 20 µA/−1.8 mA
S
0–S2
Function Select Inputs 1.0/1.0 20 µA/−0.6 mA
C
n
Carry Input 1.0/4.0 20 µA/−2.4 mA
G
Carry Generate Output (Active LOW) 50/33.3 −1 mA/20 mA
P
Carry Propagate Output (Active LOW) 50/33.3 −1 mA/20 mA
F
0–F3
Function Outputs 50/33.3 −1 mA/20 mA
Select
Operation
S
0
S
1
S
2
LLLClear
H L L B Minus A
L H L A Minus B
HHLA Plus B
LLHA⊕B
HLHA + B
LHHAB
HHHPreset
Path Segment
Toward Output
F
C
n
+ 4, OVR
A
i
or Bi to P 7.2 ns 7.2 ns
P
i
to Cn + ('F182) 6.2 ns 6.2 ns
C
n
to F 8.1 ns —
C
n
or Cn + 4, OVR — 8.0 ns
Total Delay 21.5 ns 21.4 ns
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74F381
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Inputs Outputs
Function
S
0
S
1
S
2
C
n
A
n
B
n
F
0
F
1
F
2
F
3
G P
CLEAR LLLXXXLLLLLL
LL LHHHHHL
LLHLHHHLL
LHLLLLLHH
B Minus A HL LLHHHHHHHL
HLLLLLLHL
HLHHHHHLL
HHLHL LLHH
HHHLL LLHL
LL LHHHHHL
LLHLLLLHH
LHL LHHHLL
A Minus B LHL LHHHHHHHL
HLLLLLLHL
HLHHLL LHH
HHLHHHHLL
HHHLL LLHL
LLLLLLLHH
LLHHHHHHL
LHLHHHHHL
A Plus B H H L L H H L H H H L L
HLLHLLLHH
HLHLLLLHL
HHLLLLLHL
HHHHHHHLL
XLLLLLLHH
XLHHHHHHH
A ⊕ B LLHXHLHHHHHL
XHHLLLLLL
XLLLLLLHH
XLHHHHHHH
A + B HLHXHLHHHHHH
XHHHHHHHL
XLLLLLLLL
XLHLL LLHH
AB LHHXHLLLLLLL
XHHHHHHHL
XLLHHHHHH
XLHHHHHHH
PRESET H H H X H L H H H H H H
XHHHHHHHL
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74F381
Logic Diagram
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.
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74F381
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyon d which the device
may be damaged or have its useful life impaired . Functional operation
under these condit ions is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V
CC
Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
CC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rat ed I
OL
(mA)
Free Air Ambi ent Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
V
OH
Output HIGH 10% V
CC
2.5
VMin
IOH = −1 mA
Voltage 5% V
CC
2.7 IOH = −1 mA
V
OL
Output LOW 10% V
CC
0.5 V Min IOL = 20 mA
Voltage
I
IH
Input HIGH
5.0 µAV
IN
= 2.7V
Current
I
BVI
Input HIGH Current
7.0 µAMaxVIN = 7.0V
Breakdown Test
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
IID = 1.9 µA
Test All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current −0.6 mA Max VIN = 0.5V (Sn)
−1.8 mA Max VIN = 0.5V (An, Bn)
−2.4 mA Max VIN = 0.5V (Cn)
I
OS
Output Short-Circuit Current −60 −150 mA Max V
OUT
= 0V
I
CC
Power Supply Current 59 89 mA Max
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74F381
AC Electrical Characteristics
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
t
PLH
Propagation Delay 2.5 8.1 12.0 2.5 13.0
ns
t
PHL
Cn to F
i
2.5 5.7 8.0 2.5 9.0
t
PLH
Propagation Delay 4.0 10.4 15.0 4.0 16.0
ns
t
PHL
Any A or B to Any F 3.5 8.2 11.0 3.5 12.0
t
PLH
Propagation Delay 4.5 8.3 20.5 4.5 21.5
ns
t
PHL
Si to F
i
4.0 8.2 15.0 4.0 16.0
t
PLH
Propagation Delay 3.5 6.4 10.0 3.5 11.0
ns
t
PHL
Ai or Bi to G
3.5 6.8 10.0 3.0 11.0
t
PLH
Propagation Delay 2.5 7.2 10.5 2.5 11.5
ns
t
PHL
Ai or Bi to P
3.5 6.5 9.5 3.5 10.5
t
PLH
Propagation Delay 4.0 7.8 12.0 4.0 13.0
ns
t
PHL
Si to G or P
4.5 10.2 13.5 4.5 14.5
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74F381
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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74F381 4-Bit Arithmetic Logic Unit
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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