Datasheet 74F379SJX, 74F379SJ, 74F379SCX, 74F379SC, 74F379PC Datasheet (Fairchild Semiconductor)

Page 1

May 1988 Revised August 1999

74F379 Quad Parallel Register with Enable

General Description

The 74F379 is a 4-bit register with buffered common Enable. This device is simila r to the 74F175 but features the common Enable rather than common Master Reset.

Features

■ Edge triggered D-type inputs

■ Buffered positive edge-triggered clock

■ Buffered common enab le input

■ True and complement outputs

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F379SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F379SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F379PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Page 2

www.fairchildsemi.com 2

74F379

Unit Loading/Fan Out

Functional Description

The 74F379 consists of four edge-triggered D-type flipflops with individual D inpu ts and Q and Q

outputs. The

Clock (CP) and Enable (E

) inputs are common to all flip-

flops. When the E

is input HIGH, the register will retain the

present data indep endent of the CP input. The D

and E

inputs can change when the clock is in eithe r state, provided that the recommended setup and hold times are observed.

Tr uth Table

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial



= LOW-to-HIGH Transition

NC = No Change

Logic Diagram

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA

0–D3

Data Inputs 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA Q

0–Q3

Flip-Flop Outputs 50/33.3 −1 mA/20 mA Q

0–Q3

Complement Outputs 50/33.3 −1 mA/20 mA

Inputs Outputs



XNCNC



HHL



LLH

Page 3

3 www.fairchildsemi.com

74F379

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation under these condit ions is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

(mA)

ESD Last Passing Voltage (Min) 4000V

Free Air Ambi ent Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% V

2.5 VMin

IOH = −1 mA

Voltage 5% V

2.7 IOH = −1 mA

Output LOW 10% V

0.5 V Min IOL = 20 mA

Voltage

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All Other Pins Grounded

Input LOW Current −0.6 mA Max VIN = 0.5V

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

CCL

Power Supply Current 28 40 mA Max VO = LOW

Page 4

www.fairchildsemi.com 4

74F379

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

= −55°C to +125°CTA = 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

MAX

Maximum Clock Frequency 100 140 75 100 MHz

PLH

Propagation Delay 3.5 5.0 6.5 3.0 8.5 3.5 7.5

PHL

CP to Qn, Q

5.0 6.5 8.5 4.0 10.0 5.0 9.5

Symbol Parameter

TA = +25°CTA = −55°C to +125°CTA = 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V

Min Max Min Max Min Max

tS(H) Setup Time, HIGH or LOW 3.0 4.0 3.0

tS(L) Dn to CP 3.0 4.0 3.0 tH(H) Hold Time, HIGH or LOW 1.0 2.0 1.0 tH(L) Dn to CP 1.0 2.0 1.0 tS(H) Setup Time, HIGH or LOW 6.0 8.0 6.0

tS(L) E to CP 6.0 8.0 6.0 tH(H) Hold Time, HIGH or LOW 0 0 0 tH(L) E to CP 0 0 0 tW(H) CP Pulse Width 4.0 5.0 4.0

tW(L) HIGH or LOW 5.0 7.0 5.0

Page 5

5 www.fairchildsemi.com

74F379

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

Page 6

www.fairchildsemi.com 6

74F379 Quad Parallel Register with Enable

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the user.

2. A critical component i n any compon ent of a lif e support device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com