Datasheet 74F378SJX, 74F378SJ, 74F378SCX, 74F378SC, 74F378PC Datasheet (Fairchild Semiconductor)

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April 1988 Revised August 1999

74F378 Parallel D-Type Register with Enable

General Description

The 74F378 is a 6-bit register with a buffered common Enable. This device is si mila r to the 74F174, but wi th com mon Enable rather than common Master Reset.

Features

■ 6-bit high-speed parallel register

■ Positive edge-triggered D-type inputs

■ Fully buffered common clock and enable inputs

■ Input clamp diodes limit high-s peed termination effects

■ Full TTL and CMOS compatible

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F378SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F378SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F378PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F378

Unit Loading/Fan Out

Functional Description

The 74F378 consists of six edge-triggere d D- typ e f lip -flo ps with individual D inputs and Q inputs. The Clock (CP ) and Enable (E

) inputs are common to all flip-flops.

When the E

input is LOW, new data is entered into the register on the LOW-to-HIGH tra nsitio n o f th e CP in put. When the E

input is HIGH the register will r etain the prese nt da ta

independent of the CP input.

Tr uth Table

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial



= LOW-to-HIGH Clock Transition

Logic Diagram

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

E Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA D

0–D5

Data Inputs 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA Q

0–Q5

Outputs 50/33.3 −1 mA/20 mA

Inputs Output

CP D



X No Change



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74F378

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation under these condit ions is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

(mA)

Free Air Ambi ent Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% V

2.5 VMin

IOH = −1 mA

Voltage 5% V

2.7 IOH = −1 mA

Output LOW 10% V

0.5 V Min IOL = 20 mA

Voltage

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All Other Pins Grounded

Input LOW Current −0.6 mA Max VIN = 0.5V

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

CCL

Power Supply Current 30 45 mA Max VO = LOW

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74F378

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

= −55°C to +125°CTA = 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

MAX

Maximum Input Frequency 80 100 70 80 MHz

PLH

Propagation Delay 3.0 5.5 7.5 3.0 10.0 3.0 8.5

PHL

CP to Q

3.5 6.0 8.5 3.5 10.5 3.5 9.5

Symbol Parameter

TA = +25°CTA = −55°C to +125°CTA = 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V

Min Max Min Max Min Max

tS(H) Setup Time, HIGH or LOW 4.0 5.0 4.0

tS(L) Dn to CP 4.0 5.0 4.0 tH(H) Hold Time, HIGH or LOW 0 2.0 0 tH(L) Dn to CP 0 2.0 0 tS(H) Setup Time, HIGH or LOW 6.0 4.5 6.0

tS(L)

E to CP

10.0 13.0 10.0 tH(H) Hold Time, HIGH or LOW 0 0 0 tH(L)

E to CP

000

tW(H) CP Pu l se Width 4.0 5.0 4.0

tW(L) HIGH or LOW 6.0 7.5 6.0

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74F378

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74F378 Parallel D-Type Register with Enable

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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