Datasheet 74F374MSA, 74F374CW, 74F374SJX, 74F374SJ, 74F374SCX Datasheet (Fairchild Semiconductor)

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May 1988 Revised August 1999

74F374 Octal D-Type Flip-Flop with 3-STATE Outputs

General Description

The 74F374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip- flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE

) are common to all flip-

flops.

Features

■ Edge-triggered D-type inputs

■ Buffered positive edge-triggered clock

■ 3-STATE outputs for bus-oriented applications

■ Guarante ed 4000V minimum ESD protection

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F374SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F374MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74F374PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F374

Unit Loading/Fan Out

Functional Description

The 74F374 con sists of eig ht edge- triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Outp ut Enable are com mon to all flip-flops. The eight flip-flops will store th e state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE

) LOW, the contents of the

eight flip-flops are available at the outputs. When the OE

is HIGH, the outputs go to th e high impeda nce state. Op eration of the OE

input does not affected the sta te of the flip-

flops.

Tr uth Table

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance



= LOW-to-HIGH Clock Transition

Logic Diagram

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

D0–D

Data Inputs 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA OE

3-STATE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA O

0–O7

3-STATE Outputs 150/40 (33.3) −3 mA/24 mA (20 mA)

Inputs Internal Output

CP OE



LH H



LL L

XXH X Z

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74F374

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation under these condit ions is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5 V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

(mA)

ESD Last Passing Voltage (Min) 4000V

Free Air Ambi ent Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% V

2.5

VMin

IOH = −1 mA

Voltage 10% V

2.4 IOH = −3 mA

5% V

2.7 IOH = −1 mA

5% V

2.7 IOH = −3 mA

Output LOW 10% V

0.5 V Min IOL = 24 mA

Voltage

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All Other Pins Grounded

Input LOW Current −0.6 mA Max VIN = 0.5V

OZH

Output Leakage Current 50 µAMaxV

OUT

= 2.7V

OZL

Output Leakage Current −50 µAMaxV

OUT

= 0.5V

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

Bus Drainage Test 500 µA0.0VV

OUT

= 5.25V

CCZ

Power Supply Current 55 86 mA Max VO = HIGH Z

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74F374

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

= −55°C to +125°CTA = 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

MAX

Maximum Clock Frequency 100 140 60 70 MHz

PLH

Propagation Delay 4.0 6.5 8.5 4.0 10.5 4.0 10.0

PHL

CP to O

4.0 6.5 8.5 4.0 11.0 4.0 10.0

PZH

Output Enable Time 2.0 9.0 11.5 2.0 14.0 2.0 12.5

PZL

2.0 5.8 7.5 2.0 10.0 2.0 8.5

PHZ

Output Disable Time 2.0 5.3 7.0 2.0 8.0 2.0 8.0

PLZ

1.54.35.51.57.51.56.5

Symbol Parameter

TA = +25°CTA = −55°C to +125°CTA = 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V

Min Max Min Max Min Max

tS(H) Setup Time, HIGH or LOW 2.0 2.5 2.0

tS(L) Dn to CP 2.0 2.0 2.0 tH(H) Hold Time, HIGH or LOW 2.0 2.0 2.0 tH(L) Dn to CP 2.0 2.5 2.0 tW(H) CP Pulse Width 7.0 7.0 7.0

tW(L) HIGH or LOW 6.0 6.0 6.0

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74F374

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M20B

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74F374

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

Package Number MSA20

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74F374 Octal D-Type Flip-Flop with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N20A

Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent license s are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are dev ic es or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided i n the labe li ng, can be re asonably expected to result in a significant injury to the user.

2. A critical componen t in any com ponent o f a l ife supp ort device or system whose failu re to perform can b e reasonably expected to c ause th e fa i lure of the li fe s upp or t device or system, or to affect its safety or effectiveness.

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