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© 1999 Fairchild Semiconductor Corporation DS009521 www.fairchildsemi.com
April 1988
Revised August 1999
74F366•74F368 Hex Inverter Buffer with 3-STATE Outputs
74F366•74F368
Hex Inverter Buffer with 3-STATE Outputs
Features
■ 3-STATE buffer outputs sink 64 mA
■ High-speed
■ Bus-oriented
■ High impedance npn base inputs for reduced loading
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagrams
74F366 74F368
Order Number Package Number Package Description
74F366SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F366PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F368SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F368SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F368PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74F366•74F368
Logic Symbols
IEEE/IEC
74F366
IEEE/IEC
74F368
Unit Loading/Fan Out
Function Tables
74F366 74F368
Pin Names Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
OE1, OE
2
Output Enable Input (Active LOW) 1.0/0.033 20 µA/−20 µA
I
n
Input 1.0/0.033 20 µA/−20 µA
O
n
, O
n
Outputs 600/106.6 (80) −12 mA/64 m A (48 mA)
Inputs Output
OE
1
OE
2
IO
LLLH
LLHL
XHX Z
HXX Z
Inputs Output
OE
IO
LL H
LH L
HX Z
L = LOW Voltage Level X = Immaterial
H
= HIGH Voltage Level Z = High Impedance
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74F366•74F368
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyon d which the device
may be damaged or have its useful life impaired . Functional operation
under these condit ions is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.
DC Electrical Characteristics
AC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V
CC
Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
CC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
Free Air Ambi ent Temperat ure 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
V
OH
Output HIGH 10% V
CC
2.0 V Min IOH = −15 mA
Voltage
V
OL
Output LOW 10% V
CC
0.55 V Min IOL = 64 mA
Voltage
I
IH
Input HIGH Current 20 µAMaxVIN = 2.7V
I
BVI
Input HIGH Current 100 µAMaxVIN = 7.0V
Breakdown Test
I
IL
Input LOW Current −20 µAMaxVIN = 0.5V
I
OZH
Output Leakage Current 50 µAMaxV
OUT
= 2.7V
I
OZL
Output Leakage Current −50 µAMaxV
OUT
= 0.5V
I
OS
Output Short-Circuit Current −100 −225 mA Max V
OUT
= 0V
I
CEX
Output HIGH Leakage Current 250 µAMaxV
OUT
= V
CC
I
ZZ
Bus Drainage Test 500 µA0.0VV
OUT
= 5.25V
I
CCH
Power Supply Current 20 25 mA Max VO = HIGH
I
CCL
Power Supply Current 49 62 mA Max VO = LOW
I
CCZ
Power Supply Current 35 48 mA Max VO = HIGH Z
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
Units
VCC = +5.0V CL = 50 pF
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
t
PLH
Propagation Delay 2.5 4.0 6.5 2.0 7.5
ns
t
PHL
1.01.85.01.05.5
t
PZH
Enable Time (74F366) 2.5 4.2 9.5 2.5 10.0
ns
t
PZL
2.54.29.02.59.5
t
PZH
Enable Time (74F368) 2.5 4.2 7.5 2.0 8.5
ns
t
PZL
3.05.68.53.09.0
t
PHZ
Disable Time 2.0 3.3 6.5 2.0 7.0
ns
t
PLZ
2.04.16.52.07.0
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74F366•74F368
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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74F366•74F368 Hex Inverter Buffer with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent license s are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided i n the labe li ng, can be re asonably expected to result in a significant injury to the
user.
2. A critical componen t in any com ponent o f a l ife supp ort
device or system whose failu re to perform can b e reasonably expected to c ause th e fa i lure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
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