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© 1999 Fairchild Semiconductor Corporation DS009518 www.fairchildsemi.com
April 1988
Revised August 1999
74F350 4-Bit Shifter with 3-STATE Outputs
74F350
4-Bit Shifter with 3-STAT E Outputs
General Description
The 74F350 is a specialized multiplexer that accepts a 4-bit
word and shifts it 0, 1, 2 or 3 places, as determined by two
Select (S
0
, S1) inputs. For expansion to longer words, three
linking inputs are p rovided for lower-order bits; thus tw o
packages can shift an 8-b it word, four packages a 16- bit
word, etc. Shifting by m ore than three places is accomplished by paralleling the 3-STATE outputs of different
packages and using the Output Enable (OE
) inputs as a
third Select level. With appropriate interconnections, the
74F350 can perform zero-backfill, sign-extend or endaround (barrel) shift functions.
Features
■ Linking inputs for word expansion
■ 3-STATE outputs for extending shift range
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Order Number Package Number Package Description
74F350SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F350SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F350PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
OE
S1S0O0O1O2O
3
HXXZZZZ
LLLI
0I1I2I3
LLHI−1I0I1I
2
LHLI−2I−1I0I
1
LHHI−3I−2I−1I
0
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74F350
Unit Loading/Fan Out
Functional Description
The 74F350 is operationally equivalent to a 4-input multiplexer with the inputs con nected so that the select code
causes successive one-bit shifts of the data word. This
internal connection makes it possible to perform shifts of 0,
1, 2 or 3 places on words of any length.
A 4-bit data word is introduced at the I
n
inputs and is
shifted according to the code applied to the select inputs
S
0
, S1. Outputs O0–O3 are 3-STATE, controlled by an
active LOW output en able (OE
). When OE is LOW, data
outputs will follow selected data inputs; when HIGH, the
data outputs will be forced to t he high impedance state.
This feature allows shifters to be cascaded on the same
output lines or to a co mmon bus. T he shift f uncti on can b e
logical, with zeros pulled in at either or both ends of the
shifting field; arith met i c, wh er e t he sign bit is repea ted du ring a shift down; or end around, where the data word forms
a continuous loop.
Logic Equations
O0 = S0S1I0 + S0S1I−1 + S0S1I−2 + S0S1I
−3
O1 = S0S1I1 + S0S1I0 + S0S1I−1 + S0S1I
−2
O2 = S0S1I2 + S0S1I1 + S0S1I0 + S0S1I
−1
O3 = S0S1I3 + S0S1I2 + S0S1I1 + S0S1I
0
Logic Diagram
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.
Pin Names Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
S0, S
1
Select Inputs 1.0/2.0 20 µA/−1.2 mA
I
−3–I3
Data Inputs 1.0/2.0 20 µA/−1.2 mA
OE
Output Enable Input (Active LOW) 1.0/2.0 20 µA/−1.2 mA
O
0–O3
3-STATE Outputs 150/40 (33.3) −3 mA/24 mA (20 mA)
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74F350
Applications
16-Bit Shift-Up 0 to 3 Places, Zero Backfill
Function Table
8-Bit End Around Shift 0 to 7 Places
Function Table
S
1
S
0
Shift Functi on
L L No Shift
L H Shift 1 Place
H L Shift 2 Places
H H Shift 3 Places
S
2
S
1
S
0
Shift Function
L L L No Shift
L L H Shift End Around 1
L H L Shift End Around 2
L H H Shift End Around 3
H L L Shift End Around 4
H L H Shift End Around 5
H H L Shift End Around 6
H H H Shift End Around 7
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74F350
13-Bit Twos Complement Scaler
Function Table
S
1
S
0
Scale
LL÷8
1
/
8
LH÷4
1
/
4
HL÷2 ½
H H No Change 1
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74F350
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyon d which the device
may be damaged or have its useful life impaired . Functional operation
under these condit ions is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V
CC
Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
CC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
Free Air Ambi ent Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
V
OH
Output HIGH 10% V
CC
2.5 V Min IOH = −1 mA
Voltage 10% V
CC
2.4 IOH = −3 mA
5% V
CC
2.7 IOH = −1 mA
10% V
CC
2.7 IOH = −3 mA
V
OL
Output LOW Voltage 10% V
CC
0.5 V Min IOL = 24 mA
I
IH
Input HIGH Current 5.0 µAMaxVIN = 2.7V
I
BVI
Input HIGH Current
7.0 µAMaxVIN = 7.0V
Breakdown Test
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
IID = 1.9 µA
Test All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current −1.2 mA Max VIN = 0.5V
I
OZH
Output Leakage Current 50 µAMaxV
OUT
= 2.7V
I
OZL
Output Leakage Current −50 µAMaxV
OUT
= 0.5V
I
OS
Output Short-Circuit Current −60 −150 mA Max V
OUT
= 0V
I
ZZ
Bus Drainage Test 500 µA0.0VV
OUT
= 5.25V
I
CCH
Power Supply Current 34 42 mA Max VO = HIGH
I
CCL
Power Supply Current 40 57 mA Max VO = LOW
I
CCZ
Power Supply Current 40 57 mA Max VO = HIGH Z
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74F350
AC Electrical Characteristics
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
t
PLH
Propagation Delay 3.0 4.5 6.0 3.0 7.0
ns
t
PHL
In to On 2.5 4.0 5.5 2.5 6.5
t
PLH
Propagation Delay 4.0 7.8 10.0 4.0 13.5
ns
t
PHL
Sn to On 3.0 6.5 8.5 3.0 9.5
t
PZH
Output Enable Time 2.5 5.0 7.0 2.5 8.0
ns
t
PZL
4.0 7.0 9.0 4.0 10.0
t
PHZ
Output Disable Time 2.0 3.9 5.5 2.0 6.5
t
PLZ
2.0 4.0 5.5 2.0 7.5
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74F350
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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74F350 4-Bit Shifter with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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