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© 1999 Fairchild Semiconductor Corporation DS009517 www.fairchildsemi.com
April 1988
Revised August 1999
74F323 Octal Universal Shift/Storage Register
74F323
Octal Universal Shift/Storage Register
with Synchronous Reset and Common I/O Pins
General Description
The 74F323 is an 8-bi t universal shift/storag e registe r with
3-STATE outputs. Its function i s similar to th e 74F299 with
the exception of Sync hronous Reset. Parallel load inputs
and flip-flop outputs are m ultip lexed t o mini mize pin count.
Separate serial input s an d ou tpu ts a re p ro vi ded for Q
0
and
Q
7
to allow easy cascading. Four operation modes are
possible: hold (store), shift left, shift right and parallel load.
Features
■ Common parallel I/O for reduced pin count
■ Additional serial inputs and outputs for expansion
■ Four operating modes: shift left, shift right, load and
store
■ 3-STATE outputs for bus-oriented applications
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F323SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F323PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74F323
Unit Loading/Fan Out
Functional Description
The 74F323 cont ains ei ght ed ge-trig gered D-typ e flip -flops
and the interstage logic necessary to perform synchronous
reset, shift left, shift right, parallel load and hold operations.
The type of operation is determined by S
0
and S1 as shown
in the Mode S elect Table. All flip-flop outputs ar e brought
out through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load m ode. Q
0
and Q
7
are also brough t out on other pi ns for expansion in serial
shifting of longer words.
A LOW signal on SR
overrides the Select inputs and allows
the flip-flops to be rese t by the next rising edge of CP. All
other state changes are also initiated b y th e LOW-to- HIGH
CP transition. Inputs can change when the clock is in either
state provided only th at the recomme nded setup an d hold
times, relative to the rising edge of CP, are observed.
A HIGH signal on either OE
1
or OE2 disables the 3-STATE
buffers and puts the I/O pins in the high impedance stat e.
In this condition the sh ift, load, hold and reset operatio ns
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S
0
and S1 in preparation for a para l-
lel load operation.
Mode Select Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation dela ys.
Pin Names Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA
DS
0
Serial Data Input for Right Shift 1.0/1.0 20 µA/−0.6 mA
DS
7
Serial Data Input for Left Shift 1.0/1.0 20 µA/−0.6 mA
S
0, S1
Mode Select Inputs 1.0/2.0 20 µA/−1.2 mA
SR
Synchronous Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
OE
1,
OE
2
3-STATE Output Enable Inputs (Active LOW) 1.0/1.0 20 µA/−0.6 mA
I/O
0
–I/O7Multiplexed Parallel Data Inputs 3.5/1.083 70 µA/−0.65 mA
3-STATE Parallel Data Outputs 150/40 (33.3) −3 mA/24 mA (20 mA)
Q
0, Q7
Serial Outputs 50/33.3 −1 mA/20 mA
Inputs Response
SR
S1S0CP
LXX
Synchronous Reset; Q0–Q7 = LOW
HHH
Parallel Load; I/On → Q
n
HLHShift Right; DS0 → Q0, Q0 → Q1, etc.
HHL
Shift Left; DS7 → Q7, Q7 → Q6, etc.
H L L X Hold
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74F323
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyon d which the device
may be damaged or have its useful life impaired . Functional operation
under these condit ions is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V
CC
Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
CC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the r ated I
OL
(mA)
ESD Last Passing Voltage (Min) 4000V
Free Air Ambi ent Temperat ure 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
V
OH
Output HIGH 10% VCC2.5
VMin
IOH = −1 mA (Q0, Q7)
Voltage 10% VCC2.4 IOH = −3 mA (I/On)
5% VCC2.7 IOH = −1 mA (Q0, Q7)
5% VCC2.7 IOH = −3 mA (I/On)
V
OL
Output LOW 10% V
CC
0.5
VMin
IOL = 20 mA (Q0, Q7)
Voltage 10% V
CC
0.5 IOL = 24 mA (I/On)
I
IH
Input HIGH Current 5.0 µAMaxVIN = 2.7V
I
BVI
Input HIGH Current
7.0 µAMaxVIN = 7.0V (Non I/O Inputs)
Breakdown Test
I
BVIT
Input HIGH Current
0.5 mA Max VIN = 5.5V (I/O Inputs)
Breakdown (I/O)
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
IID = 1.9 µA
Test All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current −0.6 mA Max VIN = 0.5V (CP, DS0, DS7, SR, OE1, OE2)
−1.2 mA Max VIN = 0.5V (S0, S1)
I
OS
Output Short-Circuit Current −60 −150 mA Max V
OUT
= 0V
I
ZZ
Bus Drainage Test 500 µA0.0VV
OUT
= 5.25V
I
CCH
Power Supply Current 68 95 mA Max VO = HIGH
I
CCL
Power Supply Current 68 95 mA Max VO = LOW
I
CCZ
Power Supply Current 68 95 mA Max VO = HIGH Z
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74F323
AC Electrical Characteristics
AC Operating Requirements
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
Units
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
f
MAX
Maximum Input Frequency 70 100 70 MHz
t
PLH
Propagation Delay 4.0 7.0 8.0 4.0 8.5
ns
t
PHL
CP to Q0 or Q
7
4.5 6.5 8.0 4.5 8.5
t
PLH
Propagation Delay 3.5 7.0 9.0 3.5 10.0
t
PHL
CP to I/O
n
4.0 8.5 9.0 4.0 10.0
t
PZH
Output Enable Time 3.5 6.0 8.0 3.5 9.0
ns
t
PZL
4.0 7.0 10.0 4.0 11.0
t
PHZ
Output Disable Time 2.0 4.5 6.0 2.0 7.0
t
PLZ
1.0 4.0 5.5 1.0 6.5
t
PZH
Output Enable Time 3.5 9.0 3.5 10.0
ns
t
PZL
Sn to I/O
n
4.0 10.0 4.0 11.0
t
PHZ
Output Disable Time 2.5 6.0 2.5 7.0
ns
t
PLZ
Sn to I/O
n
1.0 5.5 1.5 6.5
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
UnitsVCC = +5.0V VCC = +5.0V
Min Max Min Max
tS(H) Setup Time, HIGH or LOW 8.5 8.5
ns
tS(L) S0 or S1 to CP 8.5 8.5
tH(H) Hold Time, HIGH or LOW 0 0
tH(L) S0 or S1 to CP 0 0
tS(H) Setup Time, HIGH or LOW 5.0 5.0
ns
tS(L) I/On, DS0, DS7 to CP 5.0 5.0
tH(H) Hold Time, HIGH or LOW 2.0 2.0
tH(L) I/On, DS0, DS7 to CP 2.0 2.0
tS(H) Setup Time, HIGH or LOW 10.0 10.0
ns
tS(L) SR to CP 10.0 10.0
tH(H) Hold Time, HIGH or LOW 0 0
tH(L)
SR to CP
00
tW(H) CP Pulse Width 5.0 5.0
ns
tW(L) HIGH or LOW 5.0 5.0
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74F323
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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74F323 Octal Universal Shift/Storage Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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