Datasheet 74F299SJX, 74F299SJ, 74F299SCX, 74F299SC, 74F299PC Datasheet (Fairchild Semiconductor)

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April 1988 Revised August 1999

74F299 Octal Universal Shift/Storage Register

with Common Parallel I/O Pins

General Description

The 74F299 is an 8-bi t universal shift/storag e registe r with 3-STATE outputs. Four m odes of operation are possible: hold (store), shift left , s hift rig ht an d load data. The par allel load inputs and flip-fl op outputs are mu ltiplexed to redu ce the total number of package pins. Ad ditional outputs, Q

–

, are provided to allow easy serial cascading. A separate

active LOW Master Reset is used to reset the register.

Features

■ Common parallel I/O for reduced pin count

■ Additional serial inputs and outputs for expansion

■ Four operating modes: shift left, shift right, load and

store

■ 3-STATE outputs for bus-oriented applications

■ Guarante ed 4000V minimum ESD protection

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F299SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F299SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F299PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F299

Unit Loading/Fan Out

Functional Description

The 74F299 cont ains ei ght ed ge-trig gered D-typ e flip -flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operati on is det ermine d by S

and S1, as shown in

the Mode Sele ct Table. All flip-flop outpu ts are brou ght o ut through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load m ode. Q

and Q

are also brough t out on other pi ns for expansion in serial shifting of longer words.

A LOW signal on MR

overrides the Sele ct and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either st ate prov ided only that th e recommended setup and hold times, relative to the rising edge of CP, are observed.

A HIGH signal on either OE

or OE2 disables the 3-STATE

buffers and puts the I/O pins in the high impedance stat e. In this condition the sh ift, hold, load and reset operatio ns can still occur. The 3-STATE outputs are also disabled by HIGH signals on both S

and S1 in preparation for a para l-

lel load operation.

Mode Select Table

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial



= LOW-to-HIGH Clock Transition

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation dela ys.

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA DS

Serial Data Input for Right Shift 1.0/1.0 20 µA/−0.6 mA

Serial Data Input for Left Shift 1.0/1.0 20 µA/−0.6 mA

, S

Mode Select Inputs 1.0/2.0 20 µA/−1.2 mA

Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA

, OE

3-STATE Output Enable Inputs (Active LOW) 1.0/1.0 20 µA/−0.6 mA

I/O

–I/O

Parallel Data Inputs or 3.5/1.083 70 µA/−0.65 mA

3-STATE Parallel Outputs 150/40(33.3) −3 mA/24 mA (20 mA)

, Q

Serial Outputs 50/33.3 −1 mA/20 mA

Inputs Response

S1S0CP

L X X X Asynchronous Reset; Q

0–Q7

= LOW

HHH



Parallel Load; I/On → Q

HLHShift Right; DS0 → Q0, Q0 → Q1, etc. HHL



Shift Left; DS7 → Q7, Q7 → Q6, etc.

H L L X Hold

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74F299

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation under these condit ions is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA ESD Last Passing Voltage (Min) 4000V Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output

Current Applied to Output −0.5V to +5.5V

in LOW State (Max) twice the r ated I

(mA)

Free Air Ambi ent Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% VCC2.5 V Min IOH = −1 mA (Q0, Q7, I/On) Voltage 10% VCC2.4 IOH = −3 mA (I/On)

5% VCC2.7 IOH = −1 mA (Q0, Q7, I/On) 5% VCC2.7 IOH = −3 mA (I/On)

Output LOW 10% V

0.5 V Min IOL = 20 mA (Q0, Q7)

Voltage 10% V

0.5 IOL = 24 mA (I/On)

Input HIGH

5.0 µAMax

VIN = 2.7V (CP, DS0, DS7, S0, S1,

Current

MR, OE1, OE2)

BVI

Input HIGH Current

7.0 µAMax

VIN = 7.0V (CP, DS0, DS7, S0, S1,

Breakdown Test

MR, OE1, OE2)

BVIT

Input HIGH Current

0.5 mA Max VIN = 5.5V (I/On)

Breakdown Test (I/O)

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All Other Pins Grounded

Input LOW Current −0.6

mA Max

VIN = 0.5V (CP, DS0, DS7, MR, OE1, OE2)

−1.2 VIN = 0.5V (S0, S1)

IIH+ Output Leakage

70 µAMaxV

I/O

= 2.7V (I/On)

OZH

Current

IIL+ Output Leakage

−650 µAMaxV

I/O

= 0.5V (I/On)

OZL

Current

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

Bus Drainage Test 500 µA0.0VV

OUT

= 5.25V

CCH

Power Supply Current 68 95 mA Max VO = HIGH

CCL

Power Supply Current 68 95 mA Max VO = LOW

CCZ

Power Supply Current 68 95 mA Max VO = HIGH Z

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74F299

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

= −55°C to +125°CTA = 0 to +70°C

Units

VCC = 5.0V VCC = 5.0V VCC = 5.0V CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

MAX

Maximum Input Frequency 70 100 85 70 MHz

PLH

Propagation Delay 4.0 7.0 8.0 4.0 9.0 4.0 8.5

PHL

CP to Q0 or Q

4.56.58.04.59.54.58.5

PLH

Propagation Delay 3.5 7.0 9.0 3.5 10.0 3.5 10.0

PHL

CP to I/O

4.0 8.5 9.0 4.0 11.0 4.0 10.0

PHL

Propagation Delay

5.5 7.5 9.5 5.5 12.5 5.5 10.5 ns

MR to Q0 or Q

PHL

Propagation Delay

5.5 11.0 10.0 5.5 12.0 5.5 10.5

MR to I/O

PZH

Output Enable Time 3.5 6.0 8.0 3.0 9.5 3.5 9.0

PZL

OE to I/O

4.0 7.0 10.0 4.0 13.0 4.0 11.0

PHZ

Output Disable Time 2.0 4.5 6.0 1.5 7.0 2.0 7.0

PLZ

OE to I/O

1.04.05.51.06.51.06.5

PZH

Output Enable Time 3.5 9.0 3.0 10.5 3.5 10.0

PZL

Sn to I/O

4.0 10.0 4.0 13.0 4.0 11.0

PHZ

Output Disable Time 2.5 6.0 1.5 7.0 2.5 7.0

PLZ

Sn to I/O

1.5 5.5 1.0 6.5 1.5 6.5

Symbol Parameter

TA = +25°CTA = −55°C to +125°CTA = 0 to +70°C

UnitsVCC = 5.0V VCC = 5.0V VCC = 5.0V

Min Max Min Max Min Max

tS(H) Setup Time, HIGH or LOW 8.5 10.0 8.5

tS(L) S0 or S1 to CP 8.5 7.5 8.5 tH(H) Hold Time, HIGH or LOW 0 0 0 tH(L) S0 or S1 to CP 0 0 0 tS(H) Setup Time, HIGH or LOW 5.0 5.0 5.0

tS(L) I/On, DS0 or DS7 to CP 5.0 5.0 5.0 tH(H) Hold Time, HIGH or LOW 2.0 2.0 2.0 tH(L) I/On, DS0 or DS7 to CP 2.0 2.0 2.0 tW(H) CP Pulse Width 5.0 5.0 5.0

tW(L) HIGH or LOW 5.0 5.0 5.0 tW(L)

MR Pulse Width, LOW

5.0 6.0 5.0 ns

REC

Recovery Time, MR to CP

7.0 12.0 7.0 ns

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74F299

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M20B

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number MD20D

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74F299 Octal Universal Shift/Storage Register

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N20A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the user.

2. A critical component i n any compon ent of a lif e support device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort device or system, or to affect its safety or effectiveness.

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