Datasheet 74F273SJX, 74F273SJ, 74F273SCX, 74F273SC, 74F273PC Datasheet (Fairchild Semiconductor)

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April 1988 Revised August 1999

74F273 Octal D-Type Flip-Flop

General Description

The 74F273 has e ight ed ge-trig ger ed D-ty pe fl ip-fl ops wi th individual D inputs and Q outp uts. The common buffered Clock (CP) and Master Reset (MR

) inputs load and reset

(clear) all flip-flops simultaneously. The register is fully edge-t riggered. The state of each D

input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.

All outputs will be forced LOW indepe ndently of Clock or Data inputs by a LOW voltage level on the MR

input. The device is useful fo r app lication s w here the tr ue ou tput only is required and the Clock and Master Reset are common to all storage elements.

Features

■ Ideal buffer for MOS microprocessor or memory

■ Eight edge-triggered D-type flip-flops

■ Buffered common clock

■ Buffered, asynchronous Master Reset

■ See 74F377 for clock enable version

■ See 74F373 for transparent latch version

■ See 74F374 for 3-STATE version

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F273PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F273

Unit Loading/Fan Out

Mode Select-Function Table

H = HIGH Voltage Level steady state h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L = LOW Voltage Level steady sta te I = LOW Voltage Level one setup t im e prior to the LOW-to-HIGH c lock transition X = Immaterial



= LOW-to-HIGH clock transition

Logic Diagram

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

D0–D

Data Inputs 1.0/1.0 20 µA/−0.6 mA

Master Reset (Active LOW) 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA Q

0–Q7

Data Outputs 50/33.3 −1 mA/20 mA

Operating Mode

Inputs Output

Reset (Clear) L X X L Load “1” H



Load “0” H



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74F273

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation under these condit ions is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

(mA)

ESD Last Passing Voltage (min) 4000V

Free Air Ambi ent Temperat ure 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% V

2.5 VMinIOH = −1 mA

Voltage 5% V

2.7

Output LOW 10% V

0.5 VMinIOL = 20 mA

Voltage 5% V

0.5

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All other pins grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All other pins grounded

Input LOW Current −0.6 mA Max VIN = 0.5V

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

CCH

Power Supply Current 44

mA Max

CP =



CCL

Dn = MR = HIGH

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74F273

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

= −55°C to +125°CTA = 0°C to +70°C

Units

VCC = +5.0V VCC = 5.0V VCC = 5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

MAX

Maximum Clock Frequency 160 95 130 MHz

PLH

Propagation Delay 3.0 7.0 2.5 9.5 2.5 7.5

PHL

Clock to Output 4.0 9.00 3 .0 11.0 3.5 9.0

PLH

Propagation Delay

4.5 9.5 3.0 11.0 4.0 10.0 ns

PHL

MR to Output

Symbol Parameter

TA = +25°CTA = −55°C to +125°CTA = 0°C to +70°C

UnitsVCC = +5.0V VCC = 5.0V VCC = 5.0V

Min Max Min Max Min Max

tS(H) Setup Time, HIGH or LOW 3.0 3.5 3.0

tS(L) Data to CP 3.5 4.0 3.5 tH(H) Hold Time, HIGH or LOW 0.5 1.0 0.5 tH(L) Data to CP 1.0 1.0 1.0 tW(L)

MR Pulse Width, LOW

6.0 4.0 6.0 ns

tW(H) CP Pulse Width 6.0 5.0 6.0

tW(L) HIGH or LOW 6.0 5.0 6.0 t

REC

Recovery Time, MR to CP

3.0 4.5 3.5 ns

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74F273

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M20B

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74F273 Octal D-Type Flip-Flop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N20A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the user.

2. A critical component i n any compon ent of a lif e support device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort device or system, or to affect its safety or effectiveness.

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