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© 1999 Fairchild Semiconductor Corporation DS009510 www.fairchildsemi.com
April 1988
Revised August 1999
74F269 8-Bit Bidirectional Binary Counter
74F269
8-Bit Bidirectional Binary Counter
General Description
The 74F269 is a fully synchronous 8-stage up/down
counter featuring a preset capability for programmable
operation, carry lookah ead for easy cascading a nd a U/D
input to control the di re ction of c oun ti ng . Al l stat e cha ng es,
whether in counting or para llel loadi ng, are initiated by the
rising edge of the clock.
Features
■ Synchronous counting and loading
■ Built-in lookahead carry capability
■ Count frequency 100 MHz
■ Supply current 113 mA typ
■ 300 mil slimline package
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= Transition LOW-to-HIGH
Order Number Package Number Package Description
74F269SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F269SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
PE CEP CET U/D CP Function
LXXX
Parallel Load All
Flip-Flops
HH X X
Hold
HXH X
Hold (TC Held HIGH)
HL L H
Count Up
HLLL
Count Down
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74F269
Unit Loading/Fan Out
Logic Diagram
Pin Names Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
P0–P
7
Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA
PE
Parallel Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
U/D
Up-Down Count Control Input 1.0/1.0 20 µA/−0.6 mA
CEP
Count Enable Parallel Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
CET
Count Enable Trickle Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
CP Clock Input 1.0/1.0 20 µA/−0.6 mA
TC
Terminal Count Output (Active LOW) 5.0/33.3 −1 mA/20 mA
Q
0–Q7
Flip-Flop Outputs 50/33.3 −1 mA/20 mA
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74F269
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyon d which the device
may be damaged or have its useful life impaired . Functional operation
under these condit ions is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V
CC
Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
CC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the r ated I
OL
(mA)
Free Air Ambi ent Temperat ure 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
V
OH
Output HIGH 10% V
CC
2.5
VMin
IOH = −1 mA
Voltage 5% V
CC
2.7 IOH = −1 mA
V
OL
Output LOW 10% V
CC
0.5 V Min IOL = 20 mA
Voltage
I
IH
Input HIGH Current 5.0 µAMaxVIN = 2.7V
I
BVI
Input HIGH Current
7.0 µAMaxVIN = 7.0V
Breakdown Test
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage Test
4.75 V 0.0
IID = 1.9 µA,
All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current −0.6 mA Max VIN = 0.5V
I
OS
Output Short-Circuit Current −60 −150 mA Max V
OUT
= 0V
I
CCH
Power Supply Current 104 125 mA Max VO = HIGH
I
CCL
Power Supply Current 113 135 mA Max VO = LOW
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74F269
AC Electrical Characteristics
AC Operating Requirements
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
Units
VCC = +5.0V VCC = 5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
f
MAX
Maximum Clock Frequency 100 85 MHz
t
PLH
Propagation Delay 3.5 8.0 3.5 7.0
ns
t
PHL
CP to Qn (Count-Up) 4.5 10.5 4.5 11.0
t
PLH
Propagation Delay 3.5 7.5 3.5 10.0
ns
t
PHL
U/D to TC
4.5 7.5 4.5 11.0
t
PLH
Propagation Delay 3.5 7.0 3.5 10.5
ns
t
PHL
CET to TC
3.0 10.5 3.0 11.5
t
PLH
Propagation Delay 4.5 10.0 4.5 10.5
ns
t
PHL
CP to TC
5.0 10.0 4.5 10.5
t
PLH
Propagation Delay 3.5 10.5 3.5 11.0
ns
t
PHL
CP to Qn (Count-Down) 4.5 10.5 4.5 11.0
t
PLH
Propagation Delay 3.5 7.0 3.5 10.0
ns
t
PHL
CP to Qn (Load) 4.0 7.0 4.0 7.0
Symbol Parameter
TA = +25°CT
A
= 0°C to +70°C
UnitsVCC = +5.0V VCC = 5.0V
Min Max Min Max
tS(H) Setup Time, HIGH or LOW 3.5 4.0
ns
tS(L) Data to CP 3.0 3.0
tH(H) Hold Time, HIGH or LOW 1.0 2.0
tH(L) Data to CP 1.0 1.0
tS(H) Setup Time, HIGH or LOW 5.5 6.5
ns
tS(L)
PE to CP
5.5 6.5
tH(H) Hold Time, HIGH or LOW 0 0
tH(L)
PE to CP
00
tS(H) Setup Time, HIGH or LOW 6.0 6.5
ns
tS(L)
CET or CEP to CP
8.0 9.0
tH(H) Hold Time, HIGH or LOW 0 0
tH(L)
CET or CEP to CP
00
tW(H) Clock Pulse Width, HIGH or LOW 3.5 3.5
ns
tW(L) 3.5 4.0
tS(H) Setup Time, HIGH or LOW 8.0 9.5
ns
tS(L)
U/D to CP
6.0 7.0
tH(H) Hold Time, HIGH or LOW 0.0 0.0
ns
tH(L)
U/D to CP
0.0 0.0
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74F269
Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
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74F269 8-Bit Bidirectional Binary Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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