Datasheet 74F258ASJX, 74F258ASJ, 74F258ASCX, 74F258ASC, 74F258APC Datasheet (Fairchild Semiconductor)

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April 1988 Revised August 1999

74F258A Quad 2-Input Multiplexer with 3-STATE Outputs

General Description

The 74F258A is a quad 2- input multiplexer with 3-S TATE outputs. Four bits of data from two sources can be selected using a common data select input. The four outputs present the selected data in the complement (inverted) form. The outputs may be switc hed to a high impedance state with a HIGH on the common Output Enable (OE

) input, allowing the outpu ts to int erf ace directly with bus-oriented systems.

Features

■ Multiplexer expansion by tying outputs together

■ Inverting 3-STATE outputs

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F258ASC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F258ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F258APC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F258A

Unit Loading/Fan Out

Truth Table

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance

Functional Description

The 74F258A is a quad 2-input multiplexer with 3-STATE outputs. It selects fou r bits o f data from two s ources under control of a common Select input (S). When the Select input is LOW, the I

inputs are selected an d when Select

is HIGH, the I

inputs are selected. The data on the

selected inputs appe ars at the outputs in inverted form. The 74F258A is the logi c implementation of a 4-pole, 2position switch where th e position of the switch is dete rmined by the logi c levels s upplied to the Select inp ut. The logic equation for the outputs is shown below:

n = OE • (I1n • S + I0n • S)

When the Output Enable input (OE

) is HIGH, the outputs are forced to a high impedance OFF state. If the outputs of the 3-STATE devices are tied toge ther, all but one device must be in the high imped an ce sta te t o avo i d hig h cu rre nts that would exceed th e m axim um r ating s. Designers should ensure that Output Enable signals to 3-STATE devices whose outputs are tied together are designed so there is no overlap.

Logic Diagram

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

S Common Data Select Inpu t 1.0/1.0 20 µA/−0.6 mA OE

3-STATE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA

0a–I0d

Data Inputs from Source 0 1.0/1.0 20 µA/−0.6 mA

1a–I1d

Data Inputs from Source 1 1.0/1.0 20 µA/−0.6 mA

a–Zd

3-STATE Inverting Data Outputs 150/40 (33.3) −3 mA/24 mA (20 mA)

Output Select Data Output Enable Input Inputs

SI0I

HXXXZ LHXLH LHXHL LLLXH LLHXL

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74F258A

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation under these condit ions is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

(mA)

ESD Last PassingVoltage (Min) 4000V

Free Air Ambi ent Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% V

2.5

VMin

IOH = −1 mA

Voltage 10% V

2.4 IOH = −3 mA

5% V

2.7 IOH = −1 mA

5% V

2.7 IOH = −3 mA

Output LOW 10% V

0.5 V Min IOL = 24 mA

Voltage

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All Other Pins Grounded

Input LOW Current −0.6 mA Max VIN = 0.5V

OZH

Output Leakage Current 50 µAMaxV

OUT

= 2.7V

OZL

Output Leakage Current −50 µAMaxV

OUT

= 0.5V

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

Bus Drainage Test 500 µA0.0VV

OUT

= V

CCH

Power Supply Current 6.2 9.5 mA Max VO = HIGH

CCL

Power Supply Current 15.1 23 mA Max VO = LOW

CCZ

Power Supply Current 11.3 17 mA Max VO = HIGH Z

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74F258A

AC Electrical Characteristics

Symbol Parameter

TA = +25°CT

= −5°C to +125°CTA = 0°C to +70°C

Units

VCC = +5.0V VCC = 5.0V VCC = 5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

PLH

Propagation Delay 2.5 5.3 2.0 7.5 2.0 6.0

PHL

In to Z

1.0 4.0 1.0 6.0 1.0 5.0

PLH

Propagation Delay 3.0 7.5 3.0 9.5 3.0 8.5

PHL

S to Z

2.5 7.0 2.5 9.0 2.5 8.0

PZH

Output Enable Time 2.0 6.0 2.0 8.0 2.0 7.0

PZL

2.5 7.0 2.5 9.0 2.5 8.0

PHZ

Output Disable Time 2.0 6.0 1.5 7.0 2.0 7.0

PLZ

2.0 6.0 2.0 8.5 2.0 7.0

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74F258A

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74F258A Quad 2-Input Multiplexer with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the user.

2. A critical component i n any compon ent of a lif e support device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort device or system, or to affect its safety or effectiveness.

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