Datasheet 74F253SJX, 74F253SJ, 74F253SCX, 74F253SC, 74F253PC Datasheet (Fairchild Semiconductor)

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April 1988 Revised August 1999

74F253 Dual 4-Input Multiplexer with 3-STATE Outputs

General Description

The 74F253 is a dual 4-input multiplexer with 3-STATE outputs. It can select two bits of data f rom four sour ces using common select inputs. The output may be individually switched to a high impe dance state with a HIGH on the respective Output Enable (OE

) inputs, allowing the outputs

to interface directly with bus oriented systems.

Features

■ Multifunction capability

■ Non-inverting 3-STATE outputs

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F253SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F253SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F253PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F253

Unit Loading/Fan Out

Functional Description

This device contains two identical 4-input multiplexers with 3-STATE outputs. They select two bits from four sour ces selected by common Select inputs (S

, S1). The 4-input

multiplexers have individual Output Enable (OE

, OEb)

inputs which, when HIGH, force the outputs to a high impedance (High Z) st ate. This device is the logic imple mentation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic leve ls supplied to the two select inpu ts. The logic equations for the outputs are shown below:

= OEa • (I0a • S1 • S0 + I1a • S1 • S0 +

• S1 • S0 + I3a • S1 • S0)

= OEb • (I0b • S1 • S0 + I1b • S1 • S0 +

• S1 • S0 + I3b • S1 • S0)

If the outputs of 3- STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ens ure that Outp ut Enable signals to 3STATE devices whose outputs are tied together are designed so that there is no overlap.

Tr uth Table

Address inputs S0 and S1 are common to both sections. H = HIGH Voltage Level

L = LOW Voltage Level X = Immaterial Z = High Impedance

Logic Diagram

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

I0a–I

Side A Data Inputs 1.0/1.0 20 µA/−0.6 mA

0b–I3b

Side B Data Inputs 1.0/1.0 20 µA/−0.6 mA

0–S1

Common Select Inputs 1.0/1.0 20 µA/−0.6 mA

Side A Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA

Side B Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA

, Z

3-STATE Outputs 150/40(33.3) −3 mA/24 mA (20 mA)

Select

Data Inputs

Output

Inputs Enable

0S1I0I1I2I3

OE Z

XXXXXX H Z LLLXXX L L LLHXXX L H HLXLXX L L

HLXHXX L H LHXXLX L L LHXXHX L H HHXXXL L L HHXXXH L H

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74F253

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation under these condit ions is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

(mA)

ESD Last Passing Voltage (Min) 4000V

Free Air Ambi ent Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% V

2.5

VMin

IOH = −1 mA

Voltage 10% V

2.4 IOH = −3 mA

5% V

2.7 IOH = −1 mA

5% V

2.7 IOH = −3 mA

Output LOW 10% V

0.5 V Min IOL = 24 mA

Voltage

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All Other Pins Grounded

Input LOW Current −0.6 mA Max VIN = 0.5V

OZH

Output Leakage Current 50 µAMaxV

OUT

= 2.7V

OZL

Output Leakage Current −50 µAMaxV

OUT

= 0.5V

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

−100 −225 V

OUT

= 0V

Bus Drainage Test 500 µA0.0VV

OUT

= V

CCH

Power Supply Current 11.5 16 mA Max VO = HIGH

CCL

Power Supply Current 16 23 mA Max VO = LOW

CCZ

Power Supply Current 16 23 mA Max VO = HIGH Z

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74F253

AC Electrical Characteristics

Symbol Parameter

TA = +25°CT

= −55°C to +125°CTA = 0°C to +70°C

Units

VCC = 5.0V VCC = 5.0V VCC = 5.0V CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

PLH

Propagation Delay 4.5 8.5 11.5 3.5 15.0 4.5 13.0

PHL

Sn to Z

3.0 6.5 9.0 2.5 11.0 3.0 10.0

PLH

Propagation Delay 3.0 5.5 7.0 2.5 9.0 3.0 8.0

PHL

In to Z

2.54.56.02.58.02.57.0

PZH

Output Enable Time 3.0 6.0 8.0 2.5 10.0 3.0 9.0

PZL

3.0 6.0 8.0 2.5 10.0 3.0 9.0

PHZ

Output Disable Time 2.0 3.7 5.0 2.0 6.5 2.0 6.0

PLZ

2.04.46.02.08.02.07.0

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74F253

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74F253 Dual 4-Input Multiplexer with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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