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74F253
Dual 4-Input Multiplexer with 3-STATE Outputs
74F253 Dual 4-Input Multiplexer with 3-STATE Outputs
April 1988
Revised September 2000
General Description
The 74F253 is a dual 4-input multiplexer with 3-STATE outputs. It can select two bits of data f rom four sour ces using
common select inputs. The output may be individually
switched to a high impe dance state with a HIGH on the
respective Output Enable (OE
to interface directly with bus oriented systems.
) inputs, allowing the o utp uts
Features
■ Multifunction capability
■ Non-inverting 3-STATE outputs
Ordering Code:
Order Number Package Number Package Description
74F253SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F253SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F253PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also availab le in Tape and Reel. Specify by appending the suffix letter “X” to the o rdering code.
Logic Symbols
IEEE/IEC
Connection Diagram
© 2000 Fairchild Semiconductor Corporation DS009505 www.fairchildsemi.com
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Unit Loading/Fan Out
74F253
Pin Names Description
I0a–I
I
0b–I3b
S
0–S1
OE
OE
, Z
Z
a
3a
a
b
b
Side A Data Inputs 1.0/1.0 20 µA/−0.6 mA
Side B Data Inputs 1.0/1.0 20 µA/−0.6 mA
Common Select Inputs 1.0/1.0 20 µA/−0.6 mA
Side A Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
Side B Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
3-STATE Outputs 150/40(33.3) −3 mA/24 mA (20 mA)
U.L.
HIGH/LOW
Input I
Output I
IH/IIL
OH/IOL
Functional Description
This device contains two identical 4-input multiplexers with
3-STATE out puts. They select two bits from four sources
selected by common Select inputs (S
multiplexers have individual Output Enable (OE
, S1). The 4-input
0
, OEb)
a
inputs which, when HIGH, force the outputs to a high
impedance (High Z) st ate. This device is the log ic implementation of a 2-pole, 4-posit ion sw itch, wh ere the positio n
of the switch is determined by the logi c levels supplied to
the two select inpu ts. The logic equations for the outputs
are shown below:
Z
= OEa • (I0a • S1 • S0 + I1a • S1 • S0 +
a
I2a • S1 • S0 + I3a • S1 • S0)
= OEb • (I0b • S1 • S0 + I1b • S1 • S0 +
Z
b
I2b • S1 • S0 + I3b • S1 • S0)
If the outputs of 3- STATE devices are tied together, all but
one device must be in the high impedance state to avoid
high currents that would exceed the maximum ratings.
Designers should ensure that Output Enable signals to
3-STATE devices whose outputs are tied together are
designed so that there is no overlap.
Logic Diagram
Truth Table
Select
Inputs Enable
S
0S1I0I1I2I3
Data Inputs
XXXXXX H Z
LLLXXX L L
LLHXXX L H
HLXLXX L L
HLXHXX L H
LHXXLX L L
LHXXHX L H
HHXXXL L L
HHXXXH L H
Address inputs S0 and S1 are common to both sections.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Output
OE Z
Output
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings(Note 1) Recommended Operating
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
Pin Potential to Ground Pin −0.5V to +7.0V
V
CC
Input Voltage (Note 2)
Input Current (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
Standard Output
CC
= 0V)
−0.5V to V
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
ESD Last Pa ssing Voltage (Min) 4000V
Conditions
Free Air Ambient Temperature 0
Supply Voltage
Note 1: Absolute maximum ratings are values beyond which the device
CC
may be damaged or have its useful life impaired . Functional operation
under these conditions is not implied.
Note 2: Either voltage lim it or c urrent limit is sufficient to protect inputs.
(mA)
DC Electrical Characteristics
Symbol Parameter Min Typ Max Units
V
V
V
V
V
I
I
I
V
I
I
I
I
I
I
I
I
I
IH
BVI
CEX
OD
IL
OZH
OZL
OS
ZZ
CCH
CCL
CCZ
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
IH
Input LOW Voltage 0.8 V Recognized as a LOW Signal
IL
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
CD
Output HIGH 10% V
OH
Voltage 10% V
Output LOW Voltage 10% V
OL
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
ID
Test All Other Pins Grounded
Output Leakage
Circuit Current All Other Pins Grounded
Input LOW Current −0.6 mA Max VIN = 0.5V
Output Leakage Current 50 µAMaxV
Output Leakage Current −50 µAMaxV
Output Short-Circuit Current −60 −150
Bus Drainage Test 500 µA0.0VV
Power Supply Current 11.5 16 mA Max VO = HIGH
Power Supply Current 16 23 mA Max VO = LOW
Power Supply Current 16 23 mA Max VO = HIGH Z
5% V
5% V
2.5
CC
2.4 IOH = −3 mA
CC
2.7 IOH = −1 mA
CC
2.7 IOH = −3 mA
CC
CC
4.75 V 0.0
−100 −225 V
0.5 V Min IOL = 24 mA
5.0 µAMaxVIN = 2.7V
7.0 µAMaxVIN = 7.0V
50 µAMaxV
3.75 µA0.0
mA Max
V
CC
IOH = −1 mA
VMin
OUT
IID = 1.9 µA
V
IOD
OUT
OUT
V
OUT
OUT
OUT
+4.5V to +5.5V
Conditions
= V
CC
= 150 mV
= 2.7V
= 0.5V
= 0V
= 0V
= V
CC
74F253
°C to +70°C
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AC Electrical Characteristics
74F253
Symbol Parameter
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
Propagation Delay 4.5 8.5 11.5 3.5 15.0 4.5 13.0
Sn to Z
n
Propagation Delay 3.0 5.5 7.0 2.5 9.0 3.0 8.0
In to Z
n
Output Enable Time 3.0 6.0 8.0 2.5 10.0 3.0 9.0
Output Disable Time 2.0 3.7 5.0 2.0 6.5 2.0 6.0
= +25°CT
T
A
V
= 5.0V VCC = 5.0V VCC = 5.0V
CC
= 50 pF CL = 50 pF CL = 50 pF
C
L
= −55°C to +125°CTA = 0°C to +70°C
A
Min Typ Max Min Max Min Max
3.0 6.5 9.0 2.5 11.0 3.0 10.0
2.54.56.02.58.02.57.0
3.0 6.0 8.0 2.5 10.0 3.0 9.0
2.04.46.02.08.02.07.0
Units
ns
ns
ns
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Physical Dimensions inches (millimeters) unless otherwise noted
74F253
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
74F253
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
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Package Number M16D
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
74F253 Dual 4-Input Multiplexer with 3-STATE Outputs
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the l abe ling, can be reasonably expected to result in a significant injury to the
user.
Package Number N16E
2. A critical compo nent in any com ponen t of a life s upp ort
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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