Datasheet 74F194SCX, 74F194SC, 74F194PC, 74F194CW, 74F194SJX Datasheet (Fairchild Semiconductor)

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April 1988 Revised March 2000

74F194 4-Bit Bidirectional Universal Shi ft Register

74F194 4-Bit Bidirectional Universal Shift Register

General Description

The 74F194 is a high-speed 4-bit bidirectional universal shift register. As a high-speed, multif unctional, sequential building bl oc k, i t is us ef ul in a w id e va r i ety o f ap pl i cat i o ns. I t may be used in seri al-s eria l, sh ift left, shif t r i ght , se rial- parallel, parallel-serial, and parallel-parallel data register transfers.

Features

■ Typical shift frequency of 150 MHz

■ Asynchronous master reset

■ Hold (do nothing) mode

■ Fully synchronous serial or parallel data transfers

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F194SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F194SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F194PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F194

Unit Loading/Fan Out

Functional Description

The 74F194 conta ins four edge-trigge red D-type flip-flo ps and the necessary inter stage logic to synchronously perform shift right, shift left, parallel load and hold operations. Signals applied to the Selec t (S

, S1) inputs determine the

type of operation, as shown in the Mode S elect Table. Signals on the Select, Parallel data (P

0–P3

) and Serial data

, DSL) inputs can change when the clock is in either

state, provided only th at the r ecomm ended s etup an d hol d times, with respect to the clock rising edge, a re observed. A LOW signal on Master Reset (MR

) overrides all other

inputs and forces the outputs LOW.

Mode Select Table

H (h) = HIGH Voltage Level L (l) = LOW Voltage Level pn (qn) = Lower case letters indicate the state of the referenc ed input (or output) one setup tim e prior to the LOW-to-HIGH c loc k t ransition. X = Immaterial

Logic Diagram

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

S0, S

Mode Control Inputs 1.0/1.0 20 µA/−0.6 mA

0–P3

Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA

Serial Data Input (Shift Right) 1.0/1.0 20 µA/−0.6 mA

Serial Data Input (Shift Left) 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA MR

Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA Q

0–Q3

Parallel Outputs 50/33.3 −1 mA/20 mA

Operating Inputs Outputs

Mode MR

S1S0DSRDSLPnQ0Q1Q2Q

Reset L X X X X X L L L L Hold H l l X X X q

0q1q2q3

Shift Left H h l X l X q1q2q3L

Hhl X hXq

1q2q3

Shift Right H l h l X X L q

0q1q2

Hlhh XXHq0q1q

Parallel Load H h h X X pnp0p1p2p

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74F194

Absolute Maximum Ratings(Note 1) Recomm ended Operating

Conditions

Note 1: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation under these condit ions is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) t wice the rated I

(mA)

Free Air Ambi ent Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% V

2.5 VMin

IOH = −1 mA

Voltage 5% V

2.7 IOH = −1 mA

Output LOW 10% V

0.5 IOL = 20 mA

Voltage

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All Other Pins Grounded

Input LOW Current −0.6 mA Max VIN = 0.5V

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

Power Supply Current 33 46 mA Max

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74F194

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

= −55°C to +125°CTA = 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

MAX

Maximum Shift Frequency 105 150 90 90 MHz

PLH

Propagation Delay 3.5 5.2 7.0 3.0 8.5 3.5 8.0

PHL

CP to Q

3.55.57.03.08.53.58.0

PHL

Propagation Delay

4.5 8.6 12.0 4.5 14.5 4.5 14.0 ns

MR to Q

Symbol Parameter

TA = +25°CTA = −55°C to +125°CTA = 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V

Min Max Min Max Min Max

tS(H) Setup Time, HIGH or LOW 4.0 6.0 4.0

tS(L) Pn or DSR or DSL to CP 4.0 4.0 4.0 tH(H) Hold Time, HIGH or LOW 1.0 1.5 1.0 tH(L) Pn or DSR or DSL to CP 0 1.0 1.0 tS(H) Setup Time, HIGH or LOW 10.0 10.5 11.0

tS(L) Sn to CP 8.0 8.0 8.0 tH(H) Hold Time, HIGH or LOW 0 0 0 tH(L) Sn to CP 0 0 0 tW(H) CP Pulse Width, HIGH 5.0 5.5 5.5 ns tW(L)

MR Pulse Width, LOW

5.0 5.0 5.0 ns

REC

Recovery Time MR to CP 9.0 9.0 11.0 ns

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74F194

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

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74F194

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74F194 4-Bit Bidirectional Universal Shi ft Register

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent license s are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are dev ic es or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided i n the labe li ng, can be re asonably expected to result in a significant injury to the user.

2. A critical componen t in any com ponent o f a l ife supp ort device or system whose failu re to perform can b e reasonably expected to c ause th e fa i lure of the li fe s upp or t device or system, or to affect its safety or effectiveness.

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