Datasheet 74F193SJ, 74F193SCX, 74F193SC, 74F193PC Datasheet (Fairchild Semiconductor)

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April 1988 Revised July 1999

74F193 Up/Down Binary Counter with Separate Up/Down Clocks

General Description

The 74F193 is an up/down modulo-16 binary counter. Separate Count Up and Count D own Clocks are used, an d in either counting mode the circuits operate synchronously. The outputs change stat e synchronousl y with the LO W-toHIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provid ed

that are used as the clock s for subsequen t stages withou t extra logic, thus simplifying multi-stage counter designs. Individual preset inputs allow the circuit to be used as a programmable counter. Both the Parallel Load (PL

) and the Master Reset (MR) inputs asynchronously override the clocks.

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending su ffix let te r “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F193SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 74F193SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F193PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

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74F193

Unit Loading/Fan Out

Functional Description

The 74F193 is a 4-bit binary synchronous up/down (reversible) counter. It contains four edge-triggered flip-flops, with internal gating and steering logic to provide master reset, individual preset, count up and count down operations.

A LOW-to-HIGH transition on the CP inpu t to each flip-flo p causes the output to change state. Synchronous switching, as opposed to ripp le counting, is achieved by dr iving the steering gates o f all st ages from a commo n Count U p line and a common Count Down line, thereby causing a ll state changes to be initiated simultaneously. A LOW-to-HIGH transition on the Count Up input will adva nce the count by one; a similar transition on the Count Down input will decrease the count by one. While counti ng with one cl ock input, the other sh ould be held HIGH, as indica ted in the Function Table.

The Terminal Count Up (TC

) and Terminal Count Down

(TC

) outputs are normally HIGH. When the circuit has

reached the maximum count state 15, the next HIGH-toLOW transition of the Count Up Clock will cause TC

to go

LOW. TC

will stay LOW until CPU goes HIGH agai n, th us

effectively repeating the Cou nt Up Clock, but delayed by two gate delays. Similarly, the TC

output will go LOW

when the circuit is in the zero state and the Count Down Clock goes LOW. Since the TC

outputs repeat the cl ock waveforms, they can be used as the cl ock input sign als to the next higher order circuit in a multistage counter.

= Q0 • Q1 • Q2 • Q3 • CP

TCD = Q0• Q1 • Q2 • Q3 • CP

The 74F193 has an asynchronous parallel load capability permitting the counter to be preset. When the Parallel Load (PL

) and the Master Reset ( MR) inputs ar e LOW, informa-

tion present on the Parallel Data input (P

0–P3

) is loaded

into the counter and appears on the outputs regardless of the conditions of the clock inpu ts. A HIGH signal on the Master Reset input will d isable the preset gates, ove rride both clock inputs, and latch each Q output in the LOW state. If one of t he clock inp uts is LOW du ring and aft er a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted.

Function Table

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial



= LOW-to-HIGH Clock Transition

State Diagram

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

Count Up Clock Input (Active Rising Edge) 1.0/3.0 20 µA/−1.8 mA

Count Down Clock Input (Active Rising Edge) 1.0/3.0 20 µA/−1.8 mA MR Asynchronous Master Reset Input (Active HIGH) 1.0/1.0 20 µA/−0.6 mA PL

Asynchronous Parallel Load Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA P

0–P3

Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA Q

0–Q3

Flip-Flop Outputs 50/33.3 −1 mA/20 mA TC

Terminal Count Down (Borrow) Output (Active LOW) 50/33.3 −1 mA/20 mA TC

Terminal Count Up (Carry) Output (Active LOW) 50/33.3 −1 mA/20 mA

MR PL

CPUCP

Mode

H X X X Reset (Asyn.) L L X X Preset (Asyn.) L H H H No Change LH



H Count Up

LHH



Count Down

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74F193

Logic Diagram

Please note that this d iagram is provided only f or t he understanding of lo gic operations and should not be used to estimat e propagation delays.

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74F193

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation under these conditi ons is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in put s .

DC Electrical Characteristics

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

(mA)

Free Air Ambient Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% V

2.5 VMin

IOH = −1 mA

Voltage 5% V

2.7 IOH = −1 mA

Output LOW 10% V

0.5 V Min IOL = 20 mA

Voltage

Input HIGH

5.0 Max VIN = 2.7V

Current

BVI

Input HIGH Current 100 µAMaxVIN = 7.0V Breakdown Test 7.0

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All Other Pins Grounded

Input LOW Current −0.6

mA Max

VIN = 0.5V (MR, PL, Pn)

−1.8 VIN = 0.5V (CPu, CPD)

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

Power Supply Current 38 55 mA Max

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74F193

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

= 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF

Min Typ Max Min Max

MAX

Maximum Count Frequency 100 125 90 MHz

PLH

Propagation Delay 4.0 7.0 9.0 4.0 10.0

PHL

CPU or CPD to 3.5 6.0 8.0 3.5 9.0 TCU or TC

PLH

Propagation Delay 4.0 6.5 8.5 4.0 9.5

PHL

CPU or CPD to Qn 5.5 9.5 12.5 5.5 13.5

PLH

Propagation Delay 3.0 4.5 7.0 3.0 8.0

PHL

Pn to Qn 6.0 11.0 14.5 6.0 15.5

PLH

Propagation Delay 5.0 8.5 11.0 5.0 12.0

PHL

PL to Qn

5.5 10.0 13.0 5.5 14.0

PHL

Propagation Delay 5.5 11.0 14.5 5.5 15.5 ns MR to Q

PLH

Propagation Delay 6.0 10.5 13.5 6.0 14.5 MR to TC

PHL

Propagation Delay 6.0 11.5 14.5 6.0 15.5 MR to TC

PLH

Propagation Delay 7.0 12.0 15.5 7.0 16.5

PHL

PL to TCU or TCD

7.0 11.5 14.5 7.0 15.5

PLH

Propagation Delay 7.0 11.5 14.5 7.0 15.5

PHL

Pn to TCU or TCD

6.5 11.0 14.0 6.5 15.0

Symbol Parameter

TA = +25°CT

= 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V

MinMaxMinMax

tS(H) Setup Time, HIGH or LOW 4.5 5.0

tS(L)

Pn to PL

4.5 5.0

tH(H) Hold Time, HIGH or LOW 2.0 2.0 tH(L)

Pn to PL

2.0 2.0

tW(L)

PL Pulse Width, LOW

6.0 6.0 ns

tW(L) CPU or CPD 5.0 5.0 ns

Pulse Width, LOW

tW(L) CPU or CP

Pulse Width, LOW 10.0 10.0 ns

(Change of Direction) tW(H) MR Pulse Width, HIGH 6.0 6.0 ns t

REC

Recovery Time 6.0 6.0 ns

PL to CPU or CP

REC

Recovery Time 4.0 4.0 ns

MR to CPU or CP

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74F193

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

Package Number M16A

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74F193 Up/Down Binary Counter with Separate Up/Down Clocks

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent license s are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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