Datasheet 74F174SJX, 74F174SJ, 74F174SCX, 74F174SC, 74F174PC Datasheet (Fairchild Semiconductor)

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April 1988 Revised July 1999

74F174 Hex D-Type Flip-Flop with Master Reset

General Description

The 74F174 is a high-speed hex D-type flip-flop. The device is used pr imarily as a 6-bit edge-triggered sto rage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to si multaneously clea r all flipflops.

Features

■ Edge-triggered D-type inputs

■ Buffered positive edge-triggered clock

■ Asynchronous common reset

■ Guarante ed 4000V minimum ESD protection

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F174SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F174PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F174

Unit Loading/Fan Out

Functional Description

The 74F174 consists of six edge-triggere d D- typ e f lip -flo ps with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR

) are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s output following the LOW-to-HIGH Clock (CP) tra nsition. A LOW input to the Master Reset (MR

) will force all outputs LOW independent o f Clock or Da ta inputs. Th e 74F174 is useful for applications where the true output only is required and the Clock an d Master Reset are common to all storage elements.

Tr uth Table

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial



= LOW-to-HIGH Clock Transition

Logic Diagram

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

D0–D

Data Inputs 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA MR

Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA Q

0–Q5

Outputs 50/33.3 −1 mA/20 mA

Inputs Outputs

CP D

LXXL H



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74F174

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation under these condit ions is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

(mA)

ESD Last Passing Voltage (Min) 4000V

Free Air Ambi ent T emperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% V

2.5 VMin

IOH = −1 mA

Voltage 5% V

2.7 IOH = −1 mA

Output LOW 10% V

0.5 VMin

IOL = 20 mA

Voltage 10% V

0.5 IOL = 20 mA

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All Other Pins Grounded

Input LOW Current −0.6 mA Max VIN = 0.5V

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

CCH

Power Supply Current 30 45 mA Max CP =



Dn = MR = HIGH

CCL

Power Supply Current 30 45 mA Max VO = LOW

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74F174

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

= −55°C to +125°CTA = 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

MAX

Maximum Clock Frequency 80 70 80 MHz

PLH

Propagation Delay 3.5 5.5 8.0 3.0 10.0 3.5 9.0

PHL

CP to Q

4.0 7.0 10.0 4.0 12.0 4.0 11.0

PHL

Propagation Delay

5.0 10.0 14.0 5.0 16.0 5.0 15.0 ns

MR to Q

Symbol Parameter

TA = +25°CTA = −55°C to +125° TA = 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V

Min Max Min Max Min Max

tS(H) Setup Time, HIGH or LOW 4.8 5.0 4.8 ns tS(L) Dn to CP 4.0 5.0 4.0 tH(H) Hold Time, HIGH or LOW 0 2.0 0 tH(L) Dn to CP 0 2.0 0 tW(H) CP Pulse Width 4.0 5.0 4.0

tW(L) HIGH or LOW 6.0 7.5 6.0 tW(L)

MR Pulse Width, LOW

5.0 6.5 5.0 ns

REC

Recovery Time, MR to CP 5.0 6.0 5.0

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74F174

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74F174 Hex D-Type Flip-Flop with Master Reset

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the user.

2. A critical component i n any compon ent of a lif e support device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort device or system, or to affect its safety or effectiveness.

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