Datasheet 74F169SJX, 74F169SJ, 74F169SCX, 74F169SC, 74F169PC Datasheet (Fairchild Semiconductor)

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April 1988 Revised July 1999

74F169 4-Stage Synchronous Bidirectional Counter

General Description

The 74F169 is a fully synchronous 4-stage up/down counter. The 74F169 is a modulo- 16 binary counter. Features a preset capability for programmable operation, carry lookahead for easy cascad ing and a U/D

input to control the direction of counting. All state changes, whether in counting or parallel load ing, are initiated by the LOW-toHIGH transition of the clock.

Features

■ Asynchro nous counting and loading

■ Built-in lookahead carry capability

■ Presettable for programmable operation

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F169SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F169SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F169PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F169

Unit Loading/Fan Out

Functional Description

The 74F169 uses edge-triggered J-K type flip-flops and has no constraints on changing the control or data input signals in either stat e of the c lock. The only req uireme nt is that the various inpu ts attain the desired state at least a setup time before the rising edge of the clock and rema in valid for the recom mend ed hold time therea fter. The parallel load operation t akes prece dence o ver ot her op eration s, as indicated in the Mode Select Table. When PE

is LOW,

the data on the P

0–P3

inputs enters the flip-flops on the

next rising edge of the clock. In order for counting to occur, both CEP

and CET must be LOW an d PE must be HI GH;

the U/D

input then determines the direction of counting.

The Terminal C o unt ( TC

) output is normally HIGH and goes

LOW, provided that CET

is LOW, when a counter reach es zero in the Count Down mode or reaches 15 for the 74F169 in the Count Up mode. The TC

output state is not a

function of the Count Enable Parallel (CEP

) input level.

Since the TC

signal is derived by decoding the flip-flop states, there exists the p ossibility of decoding spikes on TC

. For this reason the use of T C as a clock signal is not

recommended (see logic equations below).

1. Count Enable = CEP

• CET • PE

2. Up: (74F169): TC = Q0 • Q1 • Q2 • Q3 • (Up) • CET

3. Down: TC = Q0 • Q1 • Q2 • Q3 • (Down) • CET

Mode Select Table

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

State Diagram

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

CEP

Count Enable Parallel Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA

CET

Count Enable Trickle Input (Active LOW) 1.0/2.0 20 µA/−1.2 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA P

0–P3

Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA PE

Parallel Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA U/D

Up-Down Count Control Input 1.0/1.0 20 µA/−0.6 mA Q

0–Q3

Flip-Flop Outputs 50/33.3 −1 mA/20 mA TC

Terminal Count Output (Active LOW) 50/33.3 −1 mA/20 mA

PE CEP CET U/D

Action on Rising

Clock Edge

L X X X Load (P

→ Qn) H L L H Count Up (Increment) H L L L Count Down (Decrement) H H X X No Change (Hold) H X H X No Change (Hold)

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74F169

Logic Diagram

Please note that thes e diagrams are provide d only for the understan ding of logic operations a nd should not be used to es t im ate propagation delays.

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74F169

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation under these conditi ons is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in put s .

DC Electrical Characteristics

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the r ated I

(mA)

Free Air Ambient Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% V

2.5 VMin

IOH = −1 mA

Voltage 5% V

2.7 IOH = −1 mA

Output LOW 10% V

0.5 V Min IOL = 20 mA

Voltage

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All Other Pins Grounded

Input LOW Current −0.6

mA Max

VIN = 0.5V (except CET)

−1.2

VIN = 0.5V (CET)

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

CCL

Power Supply Current 35 52 mA Max VO = LOW

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74F169

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

= −55°C to +125°CTA = 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

MAX

Maximum Count Frequency 90 60 70 MHz

PLH

Propagation Delay 3.0 6.5 8.5 3.0 12.0 3.0 9.5

PHL

CP to Qn (PE HIGH or LOW)

4.0 9.0 11.5 4.0 16.0 4.0 13.0

PLH

Propagation Delay 5.5 12.0 15.5 5.5 20.0 5.5 17.5

PHL

CP to TC

4.0 8.5 12.5 4.0 15.0 4.0 13.0

PLH

Propagation Delay 2.5 4.5 6.5 2.5 9.0 2.5 7.0

PHL

CET to TC

2.5 8.5 11.0 2.5 12.0 2.5 12.0

PLH

Propagation Delay 3.5 8.5 11.5 3.5 16.0 3.5 12.5

PHL

U/D to TC

4.0 8.0 12.0 4.0 14.0 4.0 13.0

Symbol Parameter

TA = +25°CT

= −55°C to +125°CTA = 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V

Min Max Min Max Min Max

tS(H) Setup Time, HIGH or LOW 4.0 4.5 4.5

tS(L) Pn to CP 4.0 4.5 4.5 tH(H) Hold Time, HIGH or LOW 3.0 3.5 3.5 tH(L) Pn to CP 3.0 3.5 3.5 tS(H) Setup Time, HIGH or LOW 7.0 8.0 8.0

tS(L)

CEP or CET to CP

5.0 8.0 6.5

tH(H) Hold Time, HIGH or LOW 0 0 0 tH(L)

CEP or CET to CP

0.5 1.0 0.5

tS(H) Setup Time, HIGH or LOW 8.0 10.0 9.0

tS(L)

PE to CP

8.010.09.0

tH(H) Hold Time, HIGH or LOW 1.0 1.0 1.0 tH(L)

PE to CP

000

tS(H) Setup Time, HIGH or LOW 11.0 14.0 12.5

tS(L)

U/D to CP

7.012.08.5

tH(H) Hold Time, HIGH or LOW 0 0 0 tH(L)

U/D to CP

000

tW(H) CP Pulse Width 4.0 6.0 4.5

tW(L) HIGH or LOW 7.0 9.0 8.0

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74F169

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74F169 4-Stage Synchronous Bidirectional Counter

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent license s are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided i n the labe li ng, can be re asonably expected to result in a significant injury to the user.

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