Datasheet 74F164ASJX, 74F164ASJ, 74F164ASCX, 74F164ASC, 74F164APC Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS010613 www.fairchildsemi.com

October 1989
Revised August 1999

74F164A Serial-In, Parallel-Out Shift Register

74F164A
Serial-In, Parallel-Out Shift Register

General Description

The 74F164A is a high-speed 8-bit serial-in/parallel-out
shift register. Serial data is entered thr ough a 2-in put AND
gate synchronous wit h the LOW-to-HIGH transition of the
clock. The device features an asynchron ous Master Re set
which clears the registe r, setting all output s LOW inde pen­dent of the clock. The 74F16 4A is a faster version of the
74F164.

Features

■ Typical shift frequency of 90 MHz

■ Asynchronous Master Reset

■ Gated serial data input

■ Fully synchronous data transfers

■ 74F164A is a faster version of the 74F164

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Order Number Package Number Package Description

74F164ASC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F164ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F164APC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2

74F164A

Unit Loading/Fan Out

Functional Description

The 74F164A is a n edge-triggered 8- bit shift register with
serial data entry and an output from each of the eight
stages. Data is entere d serially through one of tw o inputs
(A or B); either of t hese inputs can be used as a n active
HIGH Enable for da ta entry through the other input. An
unused input must be tied HIGH.

Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q

0

the log-

ical AND of the two data inputs (A • B) that existed before
the rising clock edg e. A LOW level on the Master Reset
(MR

) input overrides all other inputs and clears the register

asynchronously, forcing all Q outputs LOW.

Mode Select Table

H(h) = HIGH Voltage Levels
L(l) = LOW Voltage Levels
X = Immaterial
q

n

= Lower case le tters indi cate the s tate of the referenc ed input or outpu t

one setup time prior to t he LOW-to-HIGH clock tr ansition.

Logic Diagram

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

A, B Data Inputs 1.0/1.0 20 µA/−0.6 mA
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA
MR

Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA

Q

0–Q7

Outputs 50/33.3 −1 mA/20 mA

Operating Inputs Outputs

Mode MR

AB

Q

0Q1–Q7

Reset (Clear) L X X L L-L

Hl lLq

0–q6

Shift H l h L q0–q

6

Hh l Lq0–q

6

HhhHq0–q

6

3 www.fairchildsemi.com

74F164A

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation
under these condit ions is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.

DC Electrical Characteristics

Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V

CC

Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 1) −0.5V to +7.0V
Input Current (Note 1) −30 mA to +5.0 mA
Voltage Applied to Output

in HIGH State (with V

CC

= 0V)

Standard Output −0.5V to V

CC

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)

ESD Last Passing Voltage (Min) 4000V

Free Air Ambi ent Temperat ure 0°C to +70°C
Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

V

CC

Conditions

V

IH

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized as a LOW Signal

V

CD

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

V

OH

Output HIGH 10% V

CC

2.5
VMin

IOH = −1 mA

Voltage 5% V

CC

2.7 IOH = −1 mA

V

OL

Output LOW

10% V

CC

0.5 V Min IOL = 20 mA

Voltage

I

IH

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

I

BVI

Input HIGH Current

7.0 µAMaxVIN = 7.0V

Breakdown Test

I

CEX

Output HIGH

50 µAMaxV

OUT

= V

CC

Leakage Current

V

ID

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All other pins grounded

I

OD

Output Leakage

3.75 µA0.0

V

IOD

= 150 mV

Circuit Current All other pins grounded

I

IL

Input LOW Current −0.6 mA Max VIN = 0.5V

I

OS

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

I

CC

Power Supply Current 35 55 mA Max CP = HIGH

MR = GND, A, B = GND

www.fairchildsemi.com 4

74F164A

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

A

= −55°C to +125°CTA = 0°C to +70°C

Units

VCC = +5.0V VCC = 5.0V VCC = 5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

f

MAX

Maximum Clock Frequency 80 120 60 80 MHz

t

PLH

Propagation Delay 3.0 4.8 7.5 2.5 9.0 3.0 7.5

ns

t

PHL

CP to Q

n

3.55.08.03.08.53.58.0

t

PHL

Propagation Delay

5.0 7.0 10.0 4.0 12.5 5.0 10.5 ns

MR to Q

n

Symbol Parameter

TA = +25°CTA = −55°C to +125°CTA = 0°C to +70°C

UnitsVCC = +5.0V VCC = 5.0V VCC = 5.0V

Min Max Min Max Min Max

tS(H) Setup Time, HIGH or LOW 4.5 5.5 4.5

ns

tS(L) A or B to CP 4.0 4.0 4.0
tH(H) Hold Time, HIGH or LOW 1.0 1.0 1.0
tH(L) A or B to CP 1.0 1.0 1.0
tW(H) CP Pulse Width 4.0 4.0 4.0

ns

tW(L) HIGH or LOW 7.0 7.0 7.0
tW(L)

MR Pulse Width, LOW

4.0 5.0 4.0 ns

t

REC

Recovery Time

5.0 6.5 5.0 ns

MR to CP

5 www.fairchildsemi.com

74F164A

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

Package Number M14A

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

www.fairchildsemi.com 6

74F164A Serial-In, Parallel-Out Shift Register

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be rea­sonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com