Datasheet 74F162ASCX, 74F162ASC, 74F162APC Datasheet (Fairchild Semiconductor)

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April 1988 Revised July 1999

74F160A • 74F162A Synchronous Presettable BCD Decade Counter

General Description

The 74F160A and 74F 162A are high-speed synchr onous decade counters operati ng in the BCD (8421) sequence. They are synchronously p rese tta ble fo r ap pl ica ti on s in pr ogrammable dividers. Ther e are two types of Count Ena ble inputs plus a T erminal Count output for versatility in forming synchronous multistage counters. The F160A has an asynchronous Master Rese t inp ut t hat ove rri d es all ot her inp uts and forces the outputs LOW. The F162A has a Syn chronous Reset input that overrides cou nting an d parall el loading and allows all outputs to be simultaneously reset on the rising edge of th e clock. The F160A an d F162A are high speed versions of the F160 and F162.

Features

■ Synchronous counting and loading

■ High-speed synchronous expan sion

■ Typical count rate of 120 MHz

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagrams

74F160A 74F162A

Order Number Package Number Package Description

74F160ASC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F160ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F160APC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74F162ASC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F162APC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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74F160A • 74F162A

Logic Symbols

74F160A

IEEE/IEC

74F160A

74F162A

Unit Loading/Fan Out

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

CEP Count Enable Parallel Input 1.0/1.0 20 µA/−0.6 mA CET Count Enable Trickle Input 1.0/2.0 20 µA/−1.2 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA MR

(74F160A) Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA

(74F162A) Synchronous Reset Input (Active LOW) 1.0/2.0 20 µA/−1.2 mA

0–P3

Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA

Parallel Enable Input (Active LOW) 1.0/2.0 20 µA/−1.2 mA

0–Q3

Flip-Flop Outputs 50/33.3 −1 mA/20 mA

TC Terminal Count Output 50/33.3 −1 mA/20 mA

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74F160A • 74F162A

Functional Description

The 74F160A and 74F162A cou nt modulo-10 in the BCD (8421) sequence. From st ate 9 (HLLH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a cl ock buffer. Thus all changes of the Q outputs (except due to Master Re set of the (F160A) occ ur as a result of, and synchronous with , the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (F1 60A), synchronous reset (F162A),

parallel load, count-up and hold . Five con trol in puts—Ma ster Reset (MR

, F160A), Synchronous R eset (SR, F162A),

Parallel Enable (PE

), Count Enable Parallel (CEP) and Count Enable Trickle (CET )—det ermine the mode of ope ration, as shown in the Mode Select Table. A LOW signal on MR

overrides all other inputs and asynchronously forces all

outputs LOW. A LOW signal on SR

overrides counting and parallel loading and allows all outputs to go LOW o n the next rising edge of CP. A LOW signal on PE

overrides

counting and allows information on the Parallel Data (P

)

inputs to be loade d into the flip-flops on the next rising edge of CP. With PE

and MR (F160A) or SR (F162A) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting.

The F160A and F162A use D-type edge-triggered flip-flops and changing the S R

, PE, CEP and CET inputs when the CP is in either state does not cause error s, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed.

The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 9. To implement synchronous multistage counters, the TC outputs can be used wi th the CEP and CET inputs in two different ways. Please ref er to the F568 data sheet. Th e TC o utput is su bjec t to deco ding spikes due to internal race cond itions and is therefor e not recommended for use as a clock or asynchronous reset for flip-flops, counters or re gisters. In the F160A and F162A decade counters, the TC outp ut is fully decoded and can only be HIGH in state 9. If a decade counter is preset to an illegal state, or assumes an illegal state when power is applied, it will return to the normal sequence within two counts, as shown in the State Diagram.

Logic Equations:

Count Enable = CEP × CET × PE

TC = Q0 × Q 1× Q 2 × Q3 × CET

Mode Select Table

*For 74’F162A only H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

State Diagram

Logic Diagram

Please note that this d iagram is provided only f or t he understanding of lo gic operations and should not be used to estimat e propagation delays.

*SR PE CET CEP

Action on the Rising

Clock Edge (



)

L X X X Reset (Clear)

H L X X Load (P

→ Qn) H H H H Count (Increment) H H L X No Change (Hold) H H X L No Change (Hold)

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74F160A • 74F162A

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation under these conditi ons is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in put s .

DC Electrical Characteristics

Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C V

Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output

in HIGH State (with V

= 0V)

Standard Output −0.5V to V

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

(mA)

ESD Last Passing Voltage (Min) 4000V

Free Air Ambient Temperature 0°C to +70°C Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

Conditions

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

Input LOW Voltage 0.8 V Recognized as a LOW Signal

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

Output HIGH 10% V

2.5 VMin

IOH = −1 mA

Voltage 5% V

2.7 IOH = −1 mA

Output LOW 10% V

0.5 V Min IOL = 20 mA

Voltage

Input HIGH

5.0 µAMaxVIN = 2.7V

Current

BVI

Input HIGHCurrent

7.0 µAMaxVIN = 7.0V

Breakdown Test

CEX

Output HIGH

50 µAMaxV

OUT

= V

Leakage Current

Input Leakage

4.75 V 0.0

IID = 1.9 µA

Test All Other Pins Grounded

Output Leakage

3.75 µA0.0

IOD

= 150 mV

Circuit Current All Other Pins Grounded

Input LOW −0.6 mA Max VIN = 0.5V (CP, CEP,Pn, MR (F160A)) Current −1.2 mA Max

VIN = 0.5V (CET, SR (F162A), PE)

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

Power Supply Current 37 55 mA Max VO = HIGH

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74F160A • 74F162A

AC Electrical Characteristics

AC Operating Requirements

Symbol Parameter

TA = +25°CT

= −55°C to +125°CTA = 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

MAX

Maximum Count Frequency 90 120 75 80 MHz

PLH

Propagation Delay, Count 3.5 5.5 7.5 3.5 9.0 3.5 8.5

PHL

CP to Qn (PE Input HIGH)

3.5 7.5 10.0 3.5 11.5 3.5 11.0

PLH

Propagation Delay, Load 4.0 6.0 8.5 4.0 10.0 4.0 9.5

PHL

CP to Qn (PE Input LOW)

4.0 6.0 8.5 4.0 10.0 4.0 9.5

PLH

Propagation Delay 5.0 10.0 14.0 5.0 16.5 5.0 15.0

PHL

CP to TC 5.0 10.0 14.0 5.0 15.5 5.0 15.0

PLH

Propagation Delay 2.5 4.5 7.5 2.5 9.0 2.5 8.5

PHL

CET to TC 2.5 4.5 7.5 2.5 9.0 2.5 8.5

PHL

Propagation Delay 5.5 9.0 12.0 5.5 14.0 5.5 13.0 ns MR to Qn (74F160A)

PHL

Propagation Delay 4.5 8.0 10.5 4.5 12.5 4.5 11.5 ns MR to TC (74F160A)

Symbol Parameter

TA = +25°CT

= −55°C to +125°CTA = 0°C to +70°C

UnitsVCC = +5.0V VCC = +5.0V VCC = +5.0V

Min Max Min Max Min Max

tS(H) Setup Time, HIGH or LOW 4.0 5.5 4.0

tS(L) Pn to CP (74F160A) 5.0 5.5 5.0 tS(H) Setup Time, HIGH or LOW 5.0 5.0

tS(L) Pn to CP (74F162A) 5.0 5.0 tH(H) Hold Time, HIGH or LOW 2.0 2.5 2.0 tH(L) Pn to CP 2.0 2.5 2.0 tS(H) Setup Time, HIGH or LOW 11.0 13.5 11.5

tS(L)

PE or SR to CP

8.510.59.5

tH(H) Hold Time, HIGH or LOW 2.0 2.0 2.0 tH(L)

PE or SR to CP

000

tS(H) Setup Time, HIGH or LOW 11.0 13.0 11.5

tS(L) CEP or CET to CP 5.0 6.0 5.0 tH(H) Hold Time, HIGH or LOW 0 0 0 tH(L) CEP or CET to CP 0 0 0 tW(H) Clock Pulse Width (Load) 5.0 5.0 5.0

tW(L) HIGH or LOW 5.0 5.0 5.0 tW(H) Clock Pulse Width (Count) 4.0 5.0 4.0

tW(L) HIGH or LOW 6.0 8.0 7.0 tW(L)

MR Pulse Width, LOW

5.0 5.0 5.0

(74F160A)

REC

Recovery Time 6.0 6.0 6.0 ns MR to CP (74F160A)

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74F160A • 74F162A

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74F160A • 74F162A Synchronous Presettable BCD Decade Counter

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent license s are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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