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查询74F148供应商
74F148
8-Line to 3-Line Priority Encoder
74F148 8-Line to 3-Line Priority Encoder
April 1988
Revised July 1999
General Description
The F148 provide s th re e b its of binary coded out put re presenting the positio n o f t he high est order active inp ut, alo ng
with an out p ut in di ca t i ng t he p re s en ce o f an y act i ve i np ut. I t
is easily expanded via i nput and o utput enable s to p rovi de
priority encoding over many bit s.
Features
■ Encodes eight data lines in priority
■ Provides 3-bit binary priority code
■ Input enable capability
■ Signals when data is p r esent on any input
■ Cascadable for priority encoding of n bits
Ordering Code:
Order Number Package Number Package Description
74F148SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F148SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F148PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Logic Symbols
IEEE/IEC
Connection Diagram
Truth Table
Inputs Outputs
I0I1I2I3I4I5I6I7GS A0A1A2EO
EI
HXXXXXXXXHHHHH
LHHHHHHHHH HHH L
LXXXXXXXL LLLLH
LXXXXXXLH L HLL H
LXXXXXLHH L LHLH
LXXXXLHHHL HHLH
LXXXLHHHHL LLHH
LXXLHHHHH LHLHH
LXLHHHHHH L LHH H
LLHHHHHHH LHHH H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
© 1999 Fairchild Semiconductor Corporation DS009480 www.fairchildsemi.com
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Unit Loading/Fan Out
74F148
Pin Names Description
I
0
I
1–I7
EI
EO
GS
A
0–A2
Priority Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
Priority Inputs (Active LOW) 1.0/2.0 20 µA/−1.2 mA
Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
Enable Output (Active LOW) 50/33.3 −1 mA/20 mA
Group Signal Output (Active LOW) 50/33.3 −1 mA/20 mA
Address Outputs (Active LOW) 50/33.3 −1 mA/20 mA
Functional Description
The F148 8-input priority e ncoder accept s data from eight
active LOW inputs (I
tation on the three active LOW outputs. A priority is
assigned to each input so that when two or more inputs are
simultaneously acti ve, the input with the hi ghest priority is
represented on the output, with input line 7 having the highest priority. A HIGH on the Enable Input (EI
outputs to the inactive ( HIGH) state and allow new data to
settle without pr oducing erroneous information at the out-
) and provides a binary repr esen-
0–I7
) will force all
Logic Diagram
U.L.
HIGH/LOW
puts.A Group Signal outp ut (GS
are provided along with the three priority data outputs (A
, A0). GS is active LOW when any input is LOW: this
A
1
indicates when any input is active. EO
all inputs are HIGH. Us ing the Enable Output along with
the Enable Input allows cas cading for priority en coding on
any number of inp ut signals. Both EO
inactive HIGH state when the Enable Input is HIGH.
Input I
IH/IIL
Output I
OH/IOL
) and Enable Output ( EO)
is active LOW when
and GS are in the
Application
16-Input Priority Encoder
,
2
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to est im at e propagation delays .
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Absolute Maximum Ratings(Note 1) Recommended Operating
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
Pin Potential to Ground Pin −0.5V to +7.0V
V
CC
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output −0.5V to V
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
Conditions
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyon d which the device
CC
may be damaged or have its useful life impaired . Functional operation
under these condit ions is not implied.
Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.
(mA)
DC Electrical Characteristics
74F148
Symbol Parameter Min Typ Max Units
V
V
V
V
V
I
IH
I
BVI
I
CEX
V
I
OD
I
IL
I
OS
I
CCH
I
CCL
IH
IL
CD
OH
OL
ID
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
Input LOW Voltage 0.8 V Recognized as a LOW Signal
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
Output HIGH 10% V
Voltage 5% V
Output LOW 10% V
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output High
Leakage Current
Input Leakage
Test All Other Pins Grounded
Output Leakage
Circuit Current All Other Pins Grounded
Input LOW −0.6 mA
Current −1.2 mA
Output Short-Circuit Current −60 −150 mA Max V
Power Supply Current 35 mA Max VO = HIGH
Power Supply Current 35 mA Max VO = LOW
2.5
CC
2.7 IOH = −1 mA
CC
CC
4.75 V 0.0
0.5 V Min IOL = 20 mA
5.0 µAMaxVIN = 2.7V
7.0 µAMaxVIN = 7.0V
50 µAMaxV
3.75 µA0.0
V
CC
Max
IOH = −1 mA
IID = 1.9 µA
V
VIN = 0.5V (I0, EI)
VIN = 0.5V (I1–I7)
VMin
= V
OUT
= 150 mV
IOD
= 0V
OUT
Conditions
CC
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AC Electrical Characteristics
74F148
Symbol Parameter
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Propagation Delay 3.0 7.0 9 .0 3.0 10.0
In to A
n
Propagation Delay 2.5 5.0 6 .5 2.5 7.5
In to EO
Propagation Delay 2.5 7.0 9 .0 2.5 10.0
In to GS
Propagation Delay 2.5 6.5 8 .5 2.5 9.5
EI to A
n
Propagation Delay 2.5 5.0 7 .0 2.5 8.0
EI to GS
Propagation Delay 2.5 5.5 7 .0 2.5 8.0
EI to EO
TA = +25°CT
= 0°C to +70°C
A
VCC = +5.0V VCC = +5.0V
CL = 50 pF CL = 50 pF
Min Typ Max Min Max
3.0 8.0 10.5 3.0 1 2.0
2.5 5.5 7.5 2.5 8.5
2.5 6.0 8.0 2.5 9.0
2.5 6.0 8.0 2.5 9.0
2.5 6.0 7.5 2.5 8.5
3.0 8.0 10.5 3.0 12.0
Units
ns
ns
ns
ns
ns
ns
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Physical Dimensions inches (millimeters) unless otherwise noted
74F148
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16A
Package Number M16D
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
74F148 8-Line to 3-Line Priority Encoder
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for us e of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significan t injury to the
user.
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2. A critical component in any componen t of a life su pport
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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