Datasheet 74F139SJX, 74F139SJ, 74F139SCX, 74F139SC, 74F139PC Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS009479 www.fairchildsemi.com

April 1988
Revised July 1999

74F139 Dual 1-of-4 Decoder/Demultiplexer

74F139
Dual 1-of-4 Decoder/Demultiplexer

General Description

The F139 is a high-speed, dual 1-of-4 decoder/demulti­plexer. The device has two independe nt decoders, each
accepting two inputs and provid ing four mutu ally exclus ive
active LOW outputs. Each decoder has an active LOW
Enable input which can be used as a data input for a 4-out­put demultiplexer. Each half of the F1 39 can be u sed as a
function generator pr oviding all four minte rms of two vari­ables.

Features

■ Multifunction capability

■ Two completely independent 1-of-4 decoders

■ Active LOW mutually exclusive outputs

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Truth Table

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

Order Number Package Number Package Description

74F139SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F139SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F139PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Outputs

E

A

0

A

1

O

0

O

1

O

2

O

3

HXXHHHH
LLLLHHH
LHLHLHH
LLHHHLH
LHHHHHL

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74F139

Unit Loading/Fan Out

Functional Description

The F139 is a high-speed dual 1-of-4 decoder/demulti­plexer. The device has two independent deco ders, eac h of
which accepts two binary weighted inputs (A

0–A1

) and pro-

vides four mutually exclusive active LOW Outputs (O

0–O3

).

Each decoder has an active LOW enable (E

). When E is
HIGH all outp ut s ar e f or c ed HIG H. Th e en a bl e ca n be u s ed
as the data input for a 4-output de multiplexer applicatio n.
Each half of the F139 generates all four minterms of two
variables. These four minte rm s are use f ul in so me a ppl ica ­tions, replacing multiple gate functions as shown in
Figure 1, and thereby reducing the number of packages
required in a logic network.

FIGURE 1. Gate Functions (each half)

Logic Diagram

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.

Pin Names Description

U.L.

Input I

IH/IIL

HIGH/LOW

Output I

OH/IOL

A0, A

1

Address Inputs 1.0/1.0 20 µA/−0.6 mA

E

Enable Inputs (Active LOW) 1.0/1.0 20 µA/−0.6 mA

O

0–O3

Outputs (Active LOW) 50/33.3 −1 mA/20 mA

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74F139

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyon d which the device

may be damaged or have its useful life impaired . Functional operation
under these condit ions is not implied.

Note 2: Either voltage limit or curren t limit is sufficient to protect in puts.

DC Electrical Characteristics

AC Electrical Characteristics

Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V

CC

Pin Potential to Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output

in HIGH State (with V

CC

= 0V)

Standard Output −0.5V to V

CC

3 STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated I

OL

(mA)

ESD Last Passing Voltage (Min) 4000V

Free Air Ambi ent Temper ature 0°C to +70°C
Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units

V

CC

Conditions

V

IH

Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

V

IL

Input LOW Voltage 0.8 V Recognized as a LOW Signal

V

CD

Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

V

OH

Output HIGH Voltage 10% V

CC

2.5
VMin

IOH = −1 mA

5% V

CC

2.7 IOH = −1 mA

V

OL

Output LOW Voltage 10% V

CC

0.5 V Min IOL = 20 mA

I

IH

Input HIGH Current 5.0 µAMaxVIN = 2.7V

I

BVI

Input HIGH Current Breakdown Test 7.0 µAMaxVIN = 7.0V

I

CEX

Output HIGH Leakage Current 50 µAMaxV

OUT

= V

CC

V

ID

Input Leakage Test

4.75 V 0.0

IID = 1.9 µA
All Other Pins Grounded

I

OD

Output Leakage Circuit Current

3.75 µA0.0

V

IOD

= 150 mV

All Other Pins Grounded

I

IL

Input LOW Current −0.6 mA Max VIN = 0.5V

I

OS

Output Short-Circuit Current −60 −150 mA Max V

OUT

= 0V

I

CC

Power Supply Current 13 20 mA Max

Symbol Parameter

TA = +25°CT

A

= 0°C to +70°C

Units

VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF

Min Typ Max Min Max

t

PLH

Propagation Delay 3.5 5.3 7.5 3.0 8.5

ns

t

PHL

A0 or A1 to O

n

4.06.18.04.09.0

t

PLH

Propagation Delay 3.5 5.4 7.0 3.5 8.0

ns

t

PHL

E1 to O

n

3.04.76.53.07.5

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74F139

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74F139 Dual 1-of-4 Decoder/Demultiplexer

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent license s are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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